%!PS-Adobe-3.0 %%BoundingBox: (atend) %%Pages: (atend) %%PageOrder: (atend) %%DocumentFonts: (atend) %%Creator: Frame 4.0 %%DocumentData: Clean7Bit %%EndComments %%BeginProlog % % Frame ps_prolog 4.0, for use with Frame 4.0 products % This ps_prolog file is Copyright (c) 1986-1993 Frame Technology % Corporation. All rights reserved. This ps_prolog file may be % freely copied and distributed in conjunction with documents created % using FrameMaker, FrameBuilder and FrameViewer as long as this % copyright notice is preserved. % % Frame products normally print colors as their true color on a color printer % or as shades of gray, based on luminance, on a black-and white printer. The % following flag, if set to True, forces all non-white colors to print as pure % black. This has no effect on bitmap images. /FMPrintAllColorsAsBlack false def % % Frame products can either set their own line screens or use a printer's % default settings. Three flags below control this separately for no % separations, spot separations and process separations. If a flag % is true, then the default printer settings will not be changed. If it is % false, Frame products will use their own settings from a table based on % the printer's resolution. /FMUseDefaultNoSeparationScreen true def /FMUseDefaultSpotSeparationScreen true def /FMUseDefaultProcessSeparationScreen false def % % For any given PostScript printer resolution, Frame products have two sets of % screen angles and frequencies for printing process separations, which are % recomended by Adobe. The following variable chooses the higher frequencies % when set to true or the lower frequencies when set to false. This is only % effective if the appropriate FMUseDefault...SeparationScreen flag is false. /FMUseHighFrequencyScreens true def % % PostScript Level 2 printers contain an "Accurate Screens" feature which can % improve process separation rendering at the expense of compute time. This % flag is ignored by PostScript Level 1 printers. /FMUseAcccurateScreens true def % % The following PostScript procedure defines the spot function that Frame % products will use for process separations. You may un-comment-out one of % the alternative functions below, or use your own. % % Dot function /FMSpotFunction {abs exch abs 2 copy add 1 gt {1 sub dup mul exch 1 sub dup mul add 1 sub } {dup mul exch dup mul add 1 exch sub }ifelse } def % % Line function % /FMSpotFunction { pop } def % % Elipse function % /FMSpotFunction { dup 5 mul 8 div mul exch dup mul exch add % sqrt 1 exch sub } def % % /FMversion (4.0) def /FMLevel1 /languagelevel where {pop languagelevel} {1} ifelse 2 lt def /FMPColor FMLevel1 { false /colorimage where {pop pop true} if } { true } ifelse def /FrameDict 400 dict def systemdict /errordict known not {/errordict 10 dict def errordict /rangecheck {stop} put} if % The readline in PS 23.0 doesn't recognize cr's as nl's on AppleTalk FrameDict /tmprangecheck errordict /rangecheck get put errordict /rangecheck {FrameDict /bug true put} put FrameDict /bug false put mark % Some PS machines read past the CR, so keep the following 3 lines together! currentfile 5 string readline 00 0000000000 cleartomark errordict /rangecheck FrameDict /tmprangecheck get put FrameDict /bug get { /readline { /gstring exch def /gfile exch def /gindex 0 def { gfile read pop dup 10 eq {exit} if dup 13 eq {exit} if gstring exch gindex exch put /gindex gindex 1 add def } loop pop gstring 0 gindex getinterval true } bind def } if /FMshowpage /showpage load def /FMquit /quit load def /FMFAILURE { dup = flush FMshowpage /Helvetica findfont 12 scalefont setfont 72 200 moveto show FMshowpage FMquit } def /FMVERSION { FMversion ne { (Frame product version does not match ps_prolog!) FMFAILURE } if } def /FMBADEPSF { (PostScript Lang. Ref. Man., 2nd Ed., H.2.4 says EPS must not call X ) dup dup (X) search pop exch pop exch pop length 4 -1 roll putinterval FMFAILURE } def /FMLOCAL { FrameDict begin 0 def end } def /concatprocs { /proc2 exch cvlit def/proc1 exch cvlit def/newproc proc1 length proc2 length add array def newproc 0 proc1 putinterval newproc proc1 length proc2 putinterval newproc cvx }def FrameDict begin /FMnone 0 def /FMcyan 1 def /FMmagenta 2 def /FMyellow 3 def /FMblack 4 def /FMcustom 5 def /FrameNegative false def /FrameSepIs FMnone def /FrameSepBlack 0 def /FrameSepYellow 0 def /FrameSepMagenta 0 def /FrameSepCyan 0 def /FrameSepRed 1 def /FrameSepGreen 1 def /FrameSepBlue 1 def /FrameCurGray 1 def /FrameCurPat null def /FrameCurColors [ 0 0 0 1 0 0 0 ] def /FrameColorEpsilon .001 def /eqepsilon { sub dup 0 lt {neg} if FrameColorEpsilon le } bind def /FrameCmpColorsCMYK { 2 copy 0 get exch 0 get eqepsilon { 2 copy 1 get exch 1 get eqepsilon { 2 copy 2 get exch 2 get eqepsilon { 3 get exch 3 get eqepsilon } {pop pop false} ifelse }{pop pop false} ifelse } {pop pop false} ifelse } bind def /FrameCmpColorsRGB { 2 copy 4 get exch 0 get eqepsilon { 2 copy 5 get exch 1 get eqepsilon { 6 get exch 2 get eqepsilon }{pop pop false} ifelse } {pop pop false} ifelse } bind def /RGBtoCMYK { 1 exch sub 3 1 roll 1 exch sub 3 1 roll 1 exch sub 3 1 roll 3 copy 2 copy le { pop } { exch pop } ifelse 2 copy le { pop } { exch pop } ifelse dup dup dup 6 1 roll 4 1 roll 7 1 roll sub 6 1 roll sub 5 1 roll sub 4 1 roll } bind def /CMYKtoRGB { dup dup 4 -1 roll add 5 1 roll 3 -1 roll add 4 1 roll add 1 exch sub dup 0 lt {pop 0} if 3 1 roll 1 exch sub dup 0 lt {pop 0} if exch 1 exch sub dup 0 lt {pop 0} if exch } bind def /FrameSepInit { 1.0 RealSetgray } bind def /FrameSetSepColor { /FrameSepBlue exch def /FrameSepGreen exch def /FrameSepRed exch def /FrameSepBlack exch def /FrameSepYellow exch def /FrameSepMagenta exch def /FrameSepCyan exch def /FrameSepIs FMcustom def setCurrentScreen } bind def /FrameSetCyan { /FrameSepBlue 1.0 def /FrameSepGreen 1.0 def /FrameSepRed 0.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 1.0 def /FrameSepIs FMcyan def setCurrentScreen } bind def /FrameSetMagenta { /FrameSepBlue 1.0 def /FrameSepGreen 0.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 1.0 def /FrameSepCyan 0.0 def /FrameSepIs FMmagenta def setCurrentScreen } bind def /FrameSetYellow { /FrameSepBlue 0.0 def /FrameSepGreen 1.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 1.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMyellow def setCurrentScreen } bind def /FrameSetBlack { /FrameSepBlue 0.0 def /FrameSepGreen 0.0 def /FrameSepRed 0.0 def /FrameSepBlack 1.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMblack def setCurrentScreen } bind def /FrameNoSep { /FrameSepIs FMnone def setCurrentScreen } bind def /FrameSetSepColors { FrameDict begin [ exch 1 add 1 roll ] /FrameSepColors exch def end } bind def /FrameColorInSepListCMYK { FrameSepColors { exch dup 3 -1 roll FrameCmpColorsCMYK { pop true exit } if } forall dup true ne {pop false} if } bind def /FrameColorInSepListRGB { FrameSepColors { exch dup 3 -1 roll FrameCmpColorsRGB { pop true exit } if } forall dup true ne {pop false} if } bind def /RealSetgray /setgray load def /RealSetrgbcolor /setrgbcolor load def /RealSethsbcolor /sethsbcolor load def end /setgray { FrameDict begin FrameSepIs FMnone eq { RealSetgray } { FrameSepIs FMblack eq { RealSetgray } { FrameSepIs FMcustom eq FrameSepRed 0 eq and FrameSepGreen 0 eq and FrameSepBlue 0 eq and { RealSetgray } { 1 RealSetgray pop } ifelse } ifelse } ifelse end } bind def /setrgbcolor { FrameDict begin FrameSepIs FMnone eq { RealSetrgbcolor } { 3 copy [ 4 1 roll ] FrameColorInSepListRGB { FrameSepBlue eq exch FrameSepGreen eq and exch FrameSepRed eq and { 0 } { 1 } ifelse } { FMPColor { RealSetrgbcolor currentcmykcolor } { RGBtoCMYK } ifelse FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind def /sethsbcolor { FrameDict begin FrameSepIs FMnone eq { RealSethsbcolor } { RealSethsbcolor currentrgbcolor setrgbcolor } ifelse end } bind def FrameDict begin /setcmykcolor where { pop /RealSetcmykcolor /setcmykcolor load def } { /RealSetcmykcolor { 4 1 roll 3 { 3 index add 0 max 1 min 1 exch sub 3 1 roll} repeat setrgbcolor pop } bind def } ifelse userdict /setcmykcolor { FrameDict begin FrameSepIs FMnone eq { RealSetcmykcolor } { 4 copy [ 5 1 roll ] FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and { 0 } { 1 } ifelse } { FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind put FMLevel1 not { /patProcDict 5 dict dup begin <0f1e3c78f0e1c387> { 3 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <0f87c3e1f0783c1e> { 3 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def <8142241818244281> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -1 -1 moveto 9 9 lineto stroke } bind def <03060c183060c081> { 1 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <8040201008040201> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def end def /patDict 15 dict dup begin /PatternType 1 def /PaintType 2 def /TilingType 3 def /BBox [ 0 0 8 8 ] def /XStep 8 def /YStep 8 def /PaintProc { begin patProcDict bstring known { patProcDict bstring get exec } { 8 8 true [1 0 0 -1 0 8] bstring imagemask } ifelse end } bind def end def } if /combineColor { FrameSepIs FMnone eq { graymode FMLevel1 or not { [/Pattern [/DeviceCMYK]] setcolorspace FrameCurColors 0 4 getinterval aload pop FrameCurPat setcolor } { FrameCurColors 3 get 1.0 ge { FrameCurGray RealSetgray } { FMPColor graymode and { 0 1 3 { FrameCurColors exch get 1 FrameCurGray sub mul } for RealSetcmykcolor } { 4 1 6 { FrameCurColors exch get graymode { 1 exch sub 1 FrameCurGray sub mul 1 exch sub } { 1.0 lt {FrameCurGray} {1} ifelse } ifelse } for RealSetrgbcolor } ifelse } ifelse } ifelse } { FrameCurColors 0 4 getinterval aload FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and FrameSepIs FMcustom eq and { FrameCurGray } { 1 } ifelse } { FrameSepIs FMblack eq {FrameCurGray 1.0 exch sub mul 1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop FrameCurGray 1.0 exch sub mul 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse graymode FMLevel1 or not { [/Pattern [/DeviceGray]] setcolorspace FrameCurPat setcolor } { graymode not FMLevel1 and { dup 1 lt {pop FrameCurGray} if } if RealSetgray } ifelse } ifelse } bind def /savematrix { orgmatrix currentmatrix pop } bind def /restorematrix { orgmatrix setmatrix } bind def /dmatrix matrix def /dpi 72 0 dmatrix defaultmatrix dtransform dup mul exch dup mul add sqrt def /freq dpi dup 72 div round dup 0 eq {pop 1} if 8 mul div def /sangle 1 0 dmatrix defaultmatrix dtransform exch atan def /dpiranges [ 2540 2400 1693 1270 1200 635 600 0 ] def /CMLowFreqs [ 100.402 94.8683 89.2289 100.402 94.8683 66.9349 63.2456 47.4342 ] def /YLowFreqs [ 95.25 90.0 84.65 95.25 90.0 70.5556 66.6667 50.0 ] def /KLowFreqs [ 89.8026 84.8528 79.8088 89.8026 84.8528 74.8355 70.7107 53.033 ] def /CLowAngles [ 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 ] def /MLowAngles [ 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 ] def /YLowTDot [ true true false true true false false false ] def /CMHighFreqs [ 133.87 126.491 133.843 108.503 102.523 100.402 94.8683 63.2456 ] def /YHighFreqs [ 127.0 120.0 126.975 115.455 109.091 95.25 90.0 60.0 ] def /KHighFreqs [ 119.737 113.137 119.713 128.289 121.218 89.8026 84.8528 63.6395 ] def /CHighAngles [ 71.5651 71.5651 71.5651 70.0169 70.0169 71.5651 71.5651 71.5651 ] def /MHighAngles [ 18.4349 18.4349 18.4349 19.9831 19.9831 18.4349 18.4349 18.4349 ] def /YHighTDot [ false false true false false true true false ] def /PatFreq [ 10.5833 10.0 9.4055 10.5833 10.0 10.5833 10.0 9.375 ] def /screenIndex { 0 1 dpiranges length 1 sub { dup dpiranges exch get 1 sub dpi le {exit} {pop} ifelse } for } bind def /getCyanScreen { FMUseHighFrequencyScreens { CHighAngles CMHighFreqs} {CLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def /getMagentaScreen { FMUseHighFrequencyScreens { MHighAngles CMHighFreqs } {MLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def /getYellowScreen { FMUseHighFrequencyScreens { YHighTDot YHighFreqs} { YLowTDot YLowFreqs } ifelse screenIndex dup 3 1 roll get 3 1 roll get { 3 div {2 { 1 add 2 div 3 mul dup floor sub 2 mul 1 sub exch} repeat FMSpotFunction } } {/FMSpotFunction load } ifelse 0.0 exch } bind def /getBlackScreen { FMUseHighFrequencyScreens { KHighFreqs } { KLowFreqs } ifelse screenIndex get 45.0 /FMSpotFunction load } bind def /getSpotScreen { getBlackScreen } bind def /getCompositeScreen { getBlackScreen } bind def /FMSetScreen FMLevel1 { /setscreen load }{ { 8 dict begin /HalftoneType 1 def /SpotFunction exch def /Angle exch def /Frequency exch def /AccurateScreens FMUseAcccurateScreens def currentdict end sethalftone } bind } ifelse def /setDefaultScreen { FMPColor { orgrxfer cvx orggxfer cvx orgbxfer cvx orgxfer cvx setcolortransfer } { orgxfer cvx settransfer } ifelse orgfreq organgle orgproc cvx setscreen } bind def /setCurrentScreen { FrameSepIs FMnone eq { FMUseDefaultNoSeparationScreen { setDefaultScreen } { getCompositeScreen FMSetScreen } ifelse } { FrameSepIs FMcustom eq { FMUseDefaultSpotSeparationScreen { setDefaultScreen } { getSpotScreen FMSetScreen } ifelse } { FMUseDefaultProcessSeparationScreen { setDefaultScreen } { FrameSepIs FMcyan eq { getCyanScreen FMSetScreen } { FrameSepIs FMmagenta eq { getMagentaScreen FMSetScreen } { FrameSepIs FMyellow eq { getYellowScreen FMSetScreen } { getBlackScreen FMSetScreen } ifelse } ifelse } ifelse } ifelse } ifelse } ifelse } bind def end /gstring FMLOCAL /gfile FMLOCAL /gindex FMLOCAL /orgrxfer FMLOCAL /orggxfer FMLOCAL /orgbxfer FMLOCAL /orgxfer FMLOCAL /orgproc FMLOCAL /orgrproc FMLOCAL /orggproc FMLOCAL /orgbproc FMLOCAL /organgle FMLOCAL /orgrangle FMLOCAL /orggangle FMLOCAL /orgbangle FMLOCAL /orgfreq FMLOCAL /orgrfreq FMLOCAL /orggfreq FMLOCAL /orgbfreq FMLOCAL /yscale FMLOCAL /xscale FMLOCAL /edown FMLOCAL /manualfeed FMLOCAL /paperheight FMLOCAL /paperwidth FMLOCAL /FMDOCUMENT { array /FMfonts exch def /#copies exch def FrameDict begin 0 ne /manualfeed exch def /paperheight exch def /paperwidth exch def 0 ne /FrameNegative exch def 0 ne /edown exch def /yscale exch def /xscale exch def FMLevel1 { manualfeed {setmanualfeed} if /FMdicttop countdictstack 1 add def /FMoptop count def setpapername manualfeed {true} {papersize} ifelse {manualpapersize} {false} ifelse {desperatepapersize} {false} ifelse { (Can't select requested paper size for Frame print job!) FMFAILURE } if count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for } {{1 dict dup /PageSize [paperwidth paperheight]put setpagedevice}stopped { (Can't select requested paper size for Frame print job!) FMFAILURE } if {1 dict dup /ManualFeed manualfeed put setpagedevice } stopped pop } ifelse FMPColor { currentcolorscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def cvlit /orgbproc exch def /orgbangle exch def /orgbfreq exch def cvlit /orggproc exch def /orggangle exch def /orggfreq exch def cvlit /orgrproc exch def /orgrangle exch def /orgrfreq exch def currentcolortransfer FrameNegative { 1 1 4 { pop { 1 exch sub } concatprocs 4 1 roll } for 4 copy setcolortransfer } if cvlit /orgxfer exch def cvlit /orgbxfer exch def cvlit /orggxfer exch def cvlit /orgrxfer exch def } { currentscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def currenttransfer FrameNegative { { 1 exch sub } concatprocs dup settransfer } if cvlit /orgxfer exch def } ifelse end } def /pagesave FMLOCAL /orgmatrix FMLOCAL /landscape FMLOCAL /pwid FMLOCAL /FMBEGINPAGE { FrameDict begin /pagesave save def 3.86 setmiterlimit /landscape exch 0 ne def landscape { 90 rotate 0 exch dup /pwid exch def neg translate pop }{ pop /pwid exch def } ifelse edown { [-1 0 0 1 pwid 0] concat } if 0 0 moveto paperwidth 0 lineto paperwidth paperheight lineto 0 paperheight lineto 0 0 lineto 1 setgray fill xscale yscale scale /orgmatrix matrix def gsave } def /FMENDPAGE { grestore pagesave restore end showpage } def /FMFONTDEFINE { FrameDict begin findfont ReEncode 1 index exch definefont FMfonts 3 1 roll put end } def /FMFILLS { FrameDict begin dup array /fillvals exch def dict /patCache exch def end } def /FMFILL { FrameDict begin fillvals 3 1 roll put end } def /FMNORMALIZEGRAPHICS { newpath 0.0 0.0 moveto 1 setlinewidth 0 setlinecap 0 0 0 sethsbcolor 0 setgray } bind def /fx FMLOCAL /fy FMLOCAL /fh FMLOCAL /fw FMLOCAL /llx FMLOCAL /lly FMLOCAL /urx FMLOCAL /ury FMLOCAL /FMBEGINEPSF { end /FMEPSF save def /showpage {} def % See Adobe's "PostScript Language Reference Manual, 2nd Edition", page 714. % "...the following operators MUST NOT be used in an EPS file:" (emphasis ours) /banddevice {(banddevice) FMBADEPSF} def /clear {(clear) FMBADEPSF} def /cleardictstack {(cleardictstack) FMBADEPSF} def /copypage {(copypage) FMBADEPSF} def /erasepage {(erasepage) FMBADEPSF} def /exitserver {(exitserver) FMBADEPSF} def /framedevice {(framedevice) FMBADEPSF} def /grestoreall {(grestoreall) FMBADEPSF} def /initclip {(initclip) FMBADEPSF} def /initgraphics {(initgraphics) FMBADEPSF} def /initmatrix {(initmatrix) FMBADEPSF} def /quit {(quit) FMBADEPSF} def /renderbands {(renderbands) FMBADEPSF} def /setglobal {(setglobal) FMBADEPSF} def /setpagedevice {(setpagedevice) FMBADEPSF} def /setshared {(setshared) FMBADEPSF} def /startjob {(startjob) FMBADEPSF} def /lettertray {(lettertray) FMBADEPSF} def /letter {(letter) FMBADEPSF} def /lettersmall {(lettersmall) FMBADEPSF} def /11x17tray {(11x17tray) FMBADEPSF} def /11x17 {(11x17) FMBADEPSF} def /ledgertray {(ledgertray) FMBADEPSF} def /ledger {(ledger) FMBADEPSF} def /legaltray {(legaltray) FMBADEPSF} def /legal {(legal) FMBADEPSF} def /statementtray {(statementtray) FMBADEPSF} def /statement {(statement) FMBADEPSF} def /executivetray {(executivetray) FMBADEPSF} def /executive {(executive) FMBADEPSF} def /a3tray {(a3tray) FMBADEPSF} def /a3 {(a3) FMBADEPSF} def /a4tray {(a4tray) FMBADEPSF} def /a4 {(a4) FMBADEPSF} def /a4small {(a4small) FMBADEPSF} def /b4tray {(b4tray) FMBADEPSF} def /b4 {(b4) FMBADEPSF} def /b5tray {(b5tray) FMBADEPSF} def /b5 {(b5) FMBADEPSF} def FMNORMALIZEGRAPHICS [/fy /fx /fh /fw /ury /urx /lly /llx] {exch def} forall fx fw 2 div add fy fh 2 div add translate rotate fw 2 div neg fh 2 div neg translate fw urx llx sub div fh ury lly sub div scale llx neg lly neg translate /FMdicttop countdictstack 1 add def /FMoptop count def } bind def /FMENDEPSF { count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for FMEPSF restore FrameDict begin } bind def FrameDict begin /setmanualfeed { %%BeginFeature *ManualFeed True statusdict /manualfeed true put %%EndFeature } bind def /max {2 copy lt {exch} if pop} bind def /min {2 copy gt {exch} if pop} bind def /inch {72 mul} def /pagedimen { paperheight sub abs 16 lt exch paperwidth sub abs 16 lt and {/papername exch def} {pop} ifelse } bind def /papersizedict FMLOCAL /setpapername { /papersizedict 14 dict def papersizedict begin /papername /unknown def /Letter 8.5 inch 11.0 inch pagedimen /LetterSmall 7.68 inch 10.16 inch pagedimen /Tabloid 11.0 inch 17.0 inch pagedimen /Ledger 17.0 inch 11.0 inch pagedimen /Legal 8.5 inch 14.0 inch pagedimen /Statement 5.5 inch 8.5 inch pagedimen /Executive 7.5 inch 10.0 inch pagedimen /A3 11.69 inch 16.5 inch pagedimen /A4 8.26 inch 11.69 inch pagedimen /A4Small 7.47 inch 10.85 inch pagedimen /B4 10.125 inch 14.33 inch pagedimen /B5 7.16 inch 10.125 inch pagedimen end } bind def /papersize { papersizedict begin /Letter {lettertray letter} def /LetterSmall {lettertray lettersmall} def /Tabloid {11x17tray 11x17} def /Ledger {ledgertray ledger} def /Legal {legaltray legal} def /Statement {statementtray statement} def /Executive {executivetray executive} def /A3 {a3tray a3} def /A4 {a4tray a4} def /A4Small {a4tray a4small} def /B4 {b4tray b4} def /B5 {b5tray b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end statusdict begin stopped end } bind def /manualpapersize { papersizedict begin /Letter {letter} def /LetterSmall {lettersmall} def /Tabloid {11x17} def /Ledger {ledger} def /Legal {legal} def /Statement {statement} def /Executive {executive} def /A3 {a3} def /A4 {a4} def /A4Small {a4small} def /B4 {b4} def /B5 {b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end stopped } bind def /desperatepapersize { statusdict /setpageparams known { paperwidth paperheight 0 1 statusdict begin {setpageparams} stopped end } {true} ifelse } bind def /DiacriticEncoding [ /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /space /exclam /quotedbl /numbersign /dollar /percent /ampersand /quotesingle /parenleft /parenright /asterisk /plus /comma /hyphen /period /slash /zero /one /two /three /four /five /six /seven /eight /nine /colon /semicolon /less /equal /greater /question /at /A /B /C /D /E /F /G /H /I /J /K /L /M /N /O /P /Q /R /S /T /U /V /W /X /Y /Z /bracketleft /backslash /bracketright /asciicircum /underscore /grave /a /b /c /d /e /f /g /h /i /j /k /l /m /n /o /p /q /r /s /t /u /v /w /x /y /z /braceleft /bar /braceright /asciitilde /.notdef /Adieresis /Aring /Ccedilla /Eacute /Ntilde /Odieresis /Udieresis /aacute /agrave /acircumflex /adieresis /atilde /aring /ccedilla /eacute /egrave /ecircumflex /edieresis /iacute /igrave /icircumflex /idieresis /ntilde /oacute /ograve /ocircumflex /odieresis /otilde /uacute /ugrave /ucircumflex /udieresis /dagger /.notdef /cent /sterling /section /bullet /paragraph /germandbls /registered /copyright /trademark /acute /dieresis /.notdef /AE /Oslash /.notdef /.notdef /.notdef /.notdef /yen /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /ordfeminine /ordmasculine /.notdef /ae /oslash /questiondown /exclamdown /logicalnot /.notdef /florin /.notdef /.notdef /guillemotleft /guillemotright /ellipsis /.notdef /Agrave /Atilde /Otilde /OE /oe /endash /emdash /quotedblleft /quotedblright /quoteleft /quoteright /.notdef /.notdef /ydieresis /Ydieresis /fraction /currency /guilsinglleft /guilsinglright /fi /fl /daggerdbl /periodcentered /quotesinglbase /quotedblbase /perthousand /Acircumflex /Ecircumflex /Aacute /Edieresis /Egrave /Iacute /Icircumflex /Idieresis /Igrave /Oacute /Ocircumflex /.notdef /Ograve /Uacute /Ucircumflex /Ugrave /dotlessi /circumflex /tilde /macron /breve /dotaccent /ring /cedilla /hungarumlaut /ogonek /caron ] def /ReEncode { dup length dict begin { 1 index /FID ne {def} {pop pop} ifelse } forall 0 eq {/Encoding DiacriticEncoding def} if currentdict end } bind def FMPColor { /BEGINBITMAPCOLOR { BITMAPCOLOR} def /BEGINBITMAPCOLORc { BITMAPCOLORc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUECOLOR } def /BEGINBITMAPTRUECOLORc { BITMAPTRUECOLORc } def } { /BEGINBITMAPCOLOR { BITMAPGRAY} def /BEGINBITMAPCOLORc { BITMAPGRAYc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUEGRAY } def /BEGINBITMAPTRUECOLORc { BITMAPTRUEGRAYc } def } ifelse /K { FMPrintAllColorsAsBlack { dup 1 eq 2 index 1 eq and 3 index 1 eq and not {7 {pop} repeat 0 0 0 1 0 0 0} if } if FrameCurColors astore pop combineColor } bind def /graymode true def /bwidth FMLOCAL /bpside FMLOCAL /bstring FMLOCAL /onbits FMLOCAL /offbits FMLOCAL /xindex FMLOCAL /yindex FMLOCAL /x FMLOCAL /y FMLOCAL /setPatternMode { FMLevel1 { /bwidth exch def /bpside exch def /bstring exch def /onbits 0 def /offbits 0 def freq sangle landscape {90 add} if {/y exch def /x exch def /xindex x 1 add 2 div bpside mul cvi def /yindex y 1 add 2 div bpside mul cvi def bstring yindex bwidth mul xindex 8 idiv add get 1 7 xindex 8 mod sub bitshift and 0 ne FrameNegative {not} if {/onbits onbits 1 add def 1} {/offbits offbits 1 add def 0} ifelse } setscreen offbits offbits onbits add div FrameNegative {1.0 exch sub} if /FrameCurGray exch def } { pop pop dup patCache exch known { patCache exch get } { dup patDict /bstring 3 -1 roll put patDict 9 PatFreq screenIndex get div dup matrix scale makepattern dup patCache 4 -1 roll 3 -1 roll put } ifelse /FrameCurGray 0 def /FrameCurPat exch def } ifelse /graymode false def combineColor } bind def /setGrayScaleMode { graymode not { /graymode true def FMLevel1 { setCurrentScreen } if } if /FrameCurGray exch def combineColor } bind def /normalize { transform round exch round exch itransform } bind def /dnormalize { dtransform round exch round exch idtransform } bind def /lnormalize { 0 dtransform exch cvi 2 idiv 2 mul 1 add exch idtransform pop } bind def /H { lnormalize setlinewidth } bind def /Z { setlinecap } bind def /PFill { graymode FMLevel1 or not { gsave 1 setgray eofill grestore } if } bind def /PStroke { graymode FMLevel1 or not { gsave 1 setgray stroke grestore } if stroke } bind def /fillvals FMLOCAL /X { fillvals exch get dup type /stringtype eq {8 1 setPatternMode} {setGrayScaleMode} ifelse } bind def /V { PFill gsave eofill grestore } bind def /Vclip { clip } bind def /Vstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /N { PStroke } bind def /Nclip { strokepath clip newpath } bind def /Nstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /M {newpath moveto} bind def /E {lineto} bind def /D {curveto} bind def /O {closepath} bind def /n FMLOCAL /L { /n exch def newpath normalize moveto 2 1 n {pop normalize lineto} for } bind def /Y { L closepath } bind def /x1 FMLOCAL /x2 FMLOCAL /y1 FMLOCAL /y2 FMLOCAL /R { /y2 exch def /x2 exch def /y1 exch def /x1 exch def x1 y1 x2 y1 x2 y2 x1 y2 4 Y } bind def /rad FMLOCAL /rarc {rad arcto } bind def /RR { /rad exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def mark newpath { x1 y1 rad add moveto x1 y2 x2 y2 rarc x2 y2 x2 y1 rarc x2 y1 x1 y1 rarc x1 y1 x1 y2 rarc closepath } stopped {x1 y1 x2 y2 R} if cleartomark } bind def /RRR { /rad exch def normalize /y4 exch def /x4 exch def normalize /y3 exch def /x3 exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def newpath normalize moveto mark { x2 y2 x3 y3 rarc x3 y3 x4 y4 rarc x4 y4 x1 y1 rarc x1 y1 x2 y2 rarc closepath } stopped {x1 y1 x2 y2 x3 y3 x4 y4 newpath moveto lineto lineto lineto closepath} if cleartomark } bind def /C { grestore gsave R clip setCurrentScreen } bind def /CP { grestore gsave Y clip setCurrentScreen } bind def /FMpointsize FMLOCAL /F { FMfonts exch get FMpointsize scalefont setfont } bind def /Q { /FMpointsize exch def F } bind def /T { moveto show } bind def /RF { rotate 0 ne {-1 1 scale} if } bind def /TF { gsave moveto RF show grestore } bind def /P { moveto 0 32 3 2 roll widthshow } bind def /PF { gsave moveto RF 0 32 3 2 roll widthshow grestore } bind def /S { moveto 0 exch ashow } bind def /SF { gsave moveto RF 0 exch ashow grestore } bind def /B { moveto 0 32 4 2 roll 0 exch awidthshow } bind def /BF { gsave moveto RF 0 32 4 2 roll 0 exch awidthshow grestore } bind def /G { gsave newpath normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath PFill fill grestore } bind def /Gstrk { savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch normalize 2 index 2 div sub exch 3 index 2 div add exch translate scale 0.0 0.0 1.0 5 3 roll arc restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /Gclip { newpath savematrix normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath clip newpath restorematrix } bind def /GG { gsave newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath PFill fill grestore } bind def /GGclip { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath clip newpath restorematrix } bind def /GGstrk { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /A { gsave savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch normalize 2 index 2 div sub exch 3 index 2 div add exch translate scale 0.0 0.0 1.0 5 3 roll arc restorematrix PStroke grestore } bind def /Aclip { newpath savematrix normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath strokepath clip newpath restorematrix } bind def /Astrk { Gstrk } bind def /AA { gsave savematrix newpath 3 index 2 div add exch 4 index 2 div sub exch normalize 3 index 2 div sub exch 4 index 2 div add exch translate rotate scale 0.0 0.0 1.0 5 3 roll arc restorematrix PStroke grestore } bind def /AAclip { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath strokepath clip newpath restorematrix } bind def /AAstrk { GGstrk } bind def /x FMLOCAL /y FMLOCAL /w FMLOCAL /h FMLOCAL /xx FMLOCAL /yy FMLOCAL /ww FMLOCAL /hh FMLOCAL /FMsaveobject FMLOCAL /FMoptop FMLOCAL /FMdicttop FMLOCAL /BEGINPRINTCODE { /FMdicttop countdictstack 1 add def /FMoptop count 7 sub def /FMsaveobject save def userdict begin /showpage {} def FMNORMALIZEGRAPHICS 3 index neg 3 index neg translate } bind def /ENDPRINTCODE { count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for FMsaveobject restore } bind def /gn { 0 { 46 mul cf read pop 32 sub dup 46 lt {exit} if 46 sub add } loop add } bind def /str FMLOCAL /cfs { /str sl string def 0 1 sl 1 sub {str exch val put} for str def } bind def /ic [ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 {0 hx} {1 hx} {2 hx} {3 hx} {4 hx} {5 hx} {6 hx} {7 hx} {8 hx} {9 hx} {10 hx} {11 hx} {12 hx} {13 hx} {14 hx} {15 hx} {16 hx} {17 hx} {18 hx} {19 hx} {gn hx} {0} {1} {2} {3} {4} {5} {6} {7} {8} {9} {10} {11} {12} {13} {14} {15} {16} {17} {18} {19} {gn} {0 wh} {1 wh} {2 wh} {3 wh} {4 wh} {5 wh} {6 wh} {7 wh} {8 wh} {9 wh} {10 wh} {11 wh} {12 wh} {13 wh} {14 wh} {gn wh} {0 bl} {1 bl} {2 bl} {3 bl} {4 bl} {5 bl} {6 bl} {7 bl} {8 bl} {9 bl} {10 bl} {11 bl} {12 bl} {13 bl} {14 bl} {gn bl} {0 fl} {1 fl} {2 fl} {3 fl} {4 fl} {5 fl} {6 fl} {7 fl} {8 fl} {9 fl} {10 fl} {11 fl} {12 fl} {13 fl} {14 fl} {gn fl} ] def /sl FMLOCAL /val FMLOCAL /ws FMLOCAL /im FMLOCAL /bs FMLOCAL /cs FMLOCAL /len FMLOCAL /pos FMLOCAL /ms { /sl exch def /val 255 def /ws cfs /im cfs /val 0 def /bs cfs /cs cfs } bind def 400 ms /ip { is 0 cf cs readline pop { ic exch get exec add } forall pop } bind def /rip { bis ris copy pop is 0 cf cs readline pop { ic exch get exec add } forall pop pop ris gis copy pop dup is exch cf cs readline pop { ic exch get exec add } forall pop pop gis bis copy pop dup add is exch cf cs readline pop { ic exch get exec add } forall pop } bind def /wh { /len exch def /pos exch def ws 0 len getinterval im pos len getinterval copy pop pos len } bind def /bl { /len exch def /pos exch def bs 0 len getinterval im pos len getinterval copy pop pos len } bind def /s1 1 string def /fl { /len exch def /pos exch def /val cf s1 readhexstring pop 0 get def pos 1 pos len add 1 sub {im exch val put} for pos len } bind def /hx { 3 copy getinterval cf exch readhexstring pop pop } bind def /h FMLOCAL /w FMLOCAL /d FMLOCAL /lb FMLOCAL /bitmapsave FMLOCAL /is FMLOCAL /cf FMLOCAL /wbytes { dup dup 24 eq { pop pop 3 mul } { 8 eq {pop} {1 eq {7 add 8 idiv} {3 add 4 idiv} ifelse} ifelse } ifelse } bind def /BEGINBITMAPBWc { 1 {} COMMONBITMAPc } bind def /BEGINBITMAPGRAYc { 8 {} COMMONBITMAPc } bind def /BEGINBITMAP2BITc { 2 {} COMMONBITMAPc } bind def /COMMONBITMAPc { /r exch def /d exch def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def r /is im 0 lb getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h d [w 0 0 h neg 0 h] {ip} image bitmapsave restore grestore } bind def /BEGINBITMAPBW { 1 {} COMMONBITMAP } bind def /BEGINBITMAPGRAY { 8 {} COMMONBITMAP } bind def /BEGINBITMAP2BIT { 2 {} COMMONBITMAP } bind def /COMMONBITMAP { /r exch def /d exch def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def r /is w d wbytes string def /cf currentfile def w h d [w 0 0 h neg 0 h] {cf is readhexstring pop} image bitmapsave restore grestore } bind def /ngrayt 256 array def /nredt 256 array def /nbluet 256 array def /ngreent 256 array def /gryt FMLOCAL /blut FMLOCAL /grnt FMLOCAL /redt FMLOCAL /indx FMLOCAL /cynu FMLOCAL /magu FMLOCAL /yelu FMLOCAL /k FMLOCAL /u FMLOCAL FMLevel1 { /colorsetup { currentcolortransfer /gryt exch def /blut exch def /grnt exch def /redt exch def 0 1 255 { /indx exch def /cynu 1 red indx get 255 div sub def /magu 1 green indx get 255 div sub def /yelu 1 blue indx get 255 div sub def /k cynu magu min yelu min def /u k currentundercolorremoval exec def % /u 0 def nredt indx 1 0 cynu u sub max sub redt exec put ngreent indx 1 0 magu u sub max sub grnt exec put nbluet indx 1 0 yelu u sub max sub blut exec put ngrayt indx 1 k currentblackgeneration exec sub gryt exec put } for {255 mul cvi nredt exch get} {255 mul cvi ngreent exch get} {255 mul cvi nbluet exch get} {255 mul cvi ngrayt exch get} setcolortransfer {pop 0} setundercolorremoval {} setblackgeneration } bind def } { /colorSetup2 { [ /Indexed /DeviceRGB 255 {dup red exch get 255 div exch dup green exch get 255 div exch blue exch get 255 div} ] setcolorspace } bind def } ifelse /tran FMLOCAL /fakecolorsetup { /tran 256 string def 0 1 255 {/indx exch def tran indx red indx get 77 mul green indx get 151 mul blue indx get 28 mul add add 256 idiv put} for currenttransfer {255 mul cvi tran exch get 255.0 div} exch concatprocs settransfer } bind def /BITMAPCOLOR { /d 8 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def FMLevel1 { colorsetup /is w d wbytes string def /cf currentfile def w h d [w 0 0 h neg 0 h] {cf is readhexstring pop} {is} {is} true 3 colorimage } { colorSetup2 /is w d wbytes string def /cf currentfile def 7 dict dup begin /ImageType 1 def /Width w def /Height h def /ImageMatrix [w 0 0 h neg 0 h] def /DataSource {cf is readhexstring pop} bind def /BitsPerComponent d def /Decode [0 255] def end image } ifelse bitmapsave restore grestore } bind def /BITMAPCOLORc { /d 8 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def FMLevel1 { colorsetup /is im 0 lb getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h d [w 0 0 h neg 0 h] {ip} {is} {is} true 3 colorimage } { colorSetup2 /is im 0 lb getinterval def ws 0 lb getinterval is copy pop /cf currentfile def 7 dict dup begin /ImageType 1 def /Width w def /Height h def /ImageMatrix [w 0 0 h neg 0 h] def /DataSource {ip} bind def /BitsPerComponent d def /Decode [0 255] def end image } ifelse bitmapsave restore grestore } bind def /BITMAPTRUECOLORc { /d 24 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def /is im 0 lb getinterval def /ris im 0 w getinterval def /gis im w w getinterval def /bis im w 2 mul w getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h 8 [w 0 0 h neg 0 h] {w rip pop ris} {gis} {bis} true 3 colorimage bitmapsave restore grestore } bind def /BITMAPTRUECOLOR { gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def /is w string def /gis w string def /bis w string def /cf currentfile def w h 8 [w 0 0 h neg 0 h] { cf is readhexstring pop } { cf gis readhexstring pop } { cf bis readhexstring pop } true 3 colorimage bitmapsave restore grestore } bind def /BITMAPTRUEGRAYc { /d 24 def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def /is im 0 lb getinterval def /ris im 0 w getinterval def /gis im w w getinterval def /bis im w 2 mul w getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h 8 [w 0 0 h neg 0 h] {w rip pop ris gis bis w gray} image bitmapsave restore grestore } bind def /ww FMLOCAL /r FMLOCAL /g FMLOCAL /b FMLOCAL /i FMLOCAL /gray { /ww exch def /b exch def /g exch def /r exch def 0 1 ww 1 sub { /i exch def r i get .299 mul g i get .587 mul b i get .114 mul add add r i 3 -1 roll floor cvi put } for r } bind def /BITMAPTRUEGRAY { gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def /is w string def /gis w string def /bis w string def /cf currentfile def w h 8 [w 0 0 h neg 0 h] { cf is readhexstring pop cf gis readhexstring pop cf bis readhexstring pop w gray} image bitmapsave restore grestore } bind def /BITMAPGRAY { 8 {fakecolorsetup} COMMONBITMAP } bind def /BITMAPGRAYc { 8 {fakecolorsetup} COMMONBITMAPc } bind def /ENDBITMAP { } bind def end /ALDsave FMLOCAL /ALDmatrix matrix def ALDmatrix currentmatrix pop /StartALD { /ALDsave save def savematrix ALDmatrix setmatrix } bind def /InALD { restorematrix } bind def /DoneALD { ALDsave restore } bind def /I { setdash } bind def /J { [] 0 setdash } bind def %%EndProlog %%BeginSetup (4.0) FMVERSION 1 1 0 0 612 792 0 1 19 FMDOCUMENT 0 0 /Times-BoldItalic FMFONTDEFINE 1 0 /Times-Roman FMFONTDEFINE 2 0 /Times-Bold FMFONTDEFINE 3 0 /Times-Italic FMFONTDEFINE 4 0 /Courier-Bold FMFONTDEFINE 5 0 /Courier FMFONTDEFINE 6 0 /Courier-Oblique FMFONTDEFINE 32 FMFILLS 0 0 FMFILL 1 0.1 FMFILL 2 0.3 FMFILL 3 0.5 FMFILL 4 0.7 FMFILL 5 0.9 FMFILL 6 0.97 FMFILL 7 1 FMFILL 8 <0f1e3c78f0e1c387> FMFILL 9 <0f87c3e1f0783c1e> FMFILL 10 FMFILL 11 FMFILL 12 <8142241818244281> FMFILL 13 <03060c183060c081> FMFILL 14 <8040201008040201> FMFILL 16 1 FMFILL 17 0.9 FMFILL 18 0.7 FMFILL 19 0.5 FMFILL 20 0.3 FMFILL 21 0.1 FMFILL 22 0.03 FMFILL 23 0 FMFILL 24 FMFILL 25 FMFILL 26 <3333333333333333> FMFILL 27 <0000ffff0000ffff> FMFILL 28 <7ebddbe7e7dbbd7e> FMFILL 29 FMFILL 30 <7fbfdfeff7fbfdfe> FMFILL %%EndSetup %%Page: "1" 1 %%BeginPaperSize: Letter %%EndPaperSize 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K J 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (1) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 1 18 Q 0 X 0 0 0 1 0 0 0 K 1.8 (PowerPC Processor binding to:) 190.55 624 P 1 24 Q 2.4 (IEEE 1275-1994) 223.81 546 P 2.4 (Standard for Boot \050Initialization,) 145.08 498 P 2.4 (Con\336guration\051 Firmware) 184.48 450 P 1 18 Q 1.8 (Revision: 1.10 DRAFT) 219.94 362 P 1.8 (Date: March 12, 1996) 224.32 326 P 0 0 0 1 0 0 0 K FMENDPAGE %%EndPage: "1" 1 %%Page: "2" 2 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (2) 535.5 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K FMENDPAGE %%EndPage: "2" 2 %%Page: "3" 3 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (3) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 0 1 0 0 0 K 1 12 Q 0 X (1) 36 711 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (2) 36 699 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (3) 36 687 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (4) 36 675 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (5) 36 663 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (6) 36 651 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (7) 36 639 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (8) 36 627 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (9) 36 615 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (10) 36 603 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (11) 36 591 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (12) 36 579 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (13) 36 567 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (14) 36 555 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (15) 36 543 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (16) 36 531 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (17) 36 519 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (18) 36 507 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (19) 36 495 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (20) 36 483 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (21) 36 471 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (22) 36 459 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (23) 36 447 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (24) 36 435 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (25) 36 423 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (26) 36 411 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (27) 36 399 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (28) 36 387 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (29) 36 375 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (30) 36 363 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (31) 36 351 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (32) 36 339 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (33) 36 327 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (34) 36 315 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (35) 36 303 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (36) 36 291 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (37) 36 279 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (38) 36 267 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (39) 36 255 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (40) 36 243 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (41) 36 231 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (42) 36 219 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (43) 36 207 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (44) 36 195 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (45) 36 183 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (46) 36 171 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (47) 36 159 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (48) 36 147 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (49) 36 135 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (50) 36 123 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (51) 36 111 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (52) 36 99 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (53) 36 87 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (54) 36 75 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (55) 36 63 T 0 0 0 1 0 0 0 K 27 72 54 720 C 0 0 612 792 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 2 18 Q 0 X 0 0 0 1 0 0 0 K 1.8 (Purpose of this PowerPC Pr) 72 708 P 1.8 (ocessor binding) 294.84 708 P 1 10 Q 1 (This document speci\336es the application of Open Firmware to a PowerPC Processor, including requirements and) 72 678.33 P 1 (practices to support unique \336rmware speci\336c to a PowerPC Processor) 72 666.33 P 1 (. The core requirements and practices) 359.02 666.33 P 1 (speci\336ed by Open Firmware must be augmented by processor) 72 654.33 P 1 (-speci\336c requirements to form a complete) 326.98 654.33 P 1 (speci\336cation for the \336rmware implementation for a PowerPC Processor. This document establishes such) 72 642.33 P 1 (additional requirements pertaining to the processor and the support required by Open Firmware.) 72 630.33 P 2 18 Q (T) 72 589 T (ask Gr) 82.35 589 T (oup Members) 134.53 589 T 1 10 Q 1 (The PowerPC Processor binding team members were the following:) 72 558.33 P 1 (Mitch Bradley) 72 539.33 P 1 (, FirmW) 130.4 539.33 P 1 (orks) 164.49 539.33 P 1 (Jordan Brown, SunSoft) 72 520.33 P 1 (Bob Cof) 72 501.33 P 1 (\336n, IBM) 106.99 501.33 P 1 (David Kahn, Sun Microsystems, Inc.) 72 482.33 P 1 (John Kingman\050editor\051, IBM) 72 463.33 P 1 (Luan Nguyen, Dr) 72 444.33 P 1 (., IBM) 143.71 444.33 P 1 (Mike Segapeli, IBM) 72 425.33 P 1 (Lilian W) 72 406.33 P 1 (alter) 108.03 406.33 P 1 (, FirePower) 125.4 406.33 P 2 18 Q (T) 72 365 T (rademarks) 82.67 365 T 1 10 Q 1 (The following terms, denoted by a registration symbol \050\250\051 or trademark symbol\050\252\051) 72 334.33 P 1 (on the \336rst occurrence in this publication, are registered trademarks or trademarks of) 72 322.33 P 1 (the companies as shown in the list below:) 72 310.33 P 2 12 Q (T) 90 291.33 T (rademark) 97.12 291.33 T (Company) 198 291.33 T 1 10 Q (PowerPC) 90 272.33 T 1 (International Business Machines Corporation) 198 272.33 P 2 18 Q (Revision History) 72 212 T 2 10 Q (Revision 1.01) 72 181.33 T (April 18,1995) 144 181.33 T 1 F (Included changes from Open Firmware Working Group Meeting of 01/25/9) 216 181.33 T 2 F (Revision 1.02) 72 157.33 T (May 5,1995) 144 157.33 T 1 F (Applied proposals 222, 223, 252, 253, 254, 258, 260, 261 and 263.) 216 157.33 T 2 F (Revision 1.03) 72 133.33 T (July 3,1995) 144 133.33 T 1 F (Edited IP description in Initial Program State Section.) 216 133.33 T (Applied proposals 255 and 267.) 216 121.33 T 2 F (Revision 1.4) 72 97.33 T (Aug. 11,1995) 144 97.33 T 1 F (Include changes from Open Firmware Working Group Meeting of 07/19/95.) 216 97.33 T (Add SMP Binding to document. Rearrange Section 1.) 216 85.33 T 0 0 0 1 0 0 0 K FMENDPAGE %%EndPage: "3" 3 %%Page: "4" 4 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (4) 535.5 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 0 1 0 0 0 K 1 12 Q 0 X (1) 27 711 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (2) 27 699 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (3) 27 687 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (4) 27 675 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (5) 27 663 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (6) 27 651 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (7) 27 639 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (8) 27 627 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (9) 27 615 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (10) 27 603 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (11) 27 591 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (12) 27 579 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (13) 27 567 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (14) 27 555 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (15) 27 543 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (16) 27 531 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (17) 27 519 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (18) 27 507 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (19) 27 495 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (20) 27 483 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (21) 27 471 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (22) 27 459 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (23) 27 447 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (24) 27 435 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (25) 27 423 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (26) 27 411 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (27) 27 399 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (28) 27 387 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (29) 27 375 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (30) 27 363 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (31) 27 351 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (32) 27 339 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (33) 27 327 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (34) 27 315 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (35) 27 303 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (36) 27 291 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (37) 27 279 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (38) 27 267 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (39) 27 255 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (40) 27 243 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (41) 27 231 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (42) 27 219 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (43) 27 207 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (44) 27 195 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (45) 27 183 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (46) 27 171 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (47) 27 159 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (48) 27 147 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (49) 27 135 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (50) 27 123 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (51) 27 111 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (52) 27 99 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (53) 27 87 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (54) 27 75 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (55) 27 63 T 0 0 0 1 0 0 0 K 0 0 612 792 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 1 10 Q 0 X 0 0 0 1 0 0 0 K (Applied Proposals 276, 277, 278.) 216 713.33 T (Removed \322Openprom\323 Section \050Moved to Platform Bindings\051.) 216 701.33 T (Changed name of \32264-bit-addressing\323 property to \32264-bit\323.) 216 689.33 T 2 F (Revision 1.5) 72 665.33 T (Sept. 14,1995) 144 665.33 T 1 F (Fixed bad cross-references. Minor editorial changes.) 216 665.33 T 2 F (Revision 1.6) 72 641.33 T (Oct. 27,1995) 144 641.33 T 1 F 1.5 (Included changes from Open Firmware Working Group Meeting of 09/20/95.) 216 641.33 P 1.55 (Fixed errata. Added new ELF Section. Corrected format of MP Section \050CIS) 216 629.33 P (Calls\051.) 216 617.33 T 2 F (Revision 1.7) 72 593.33 T (Jan. 12,1996) 144 593.33 T 1 F (Review Draft. Not formally released.) 216 593.33 T 2 F (Revision 1.8) 72 569.33 T (Feb. 8,1996) 144 569.33 T 1 F (Included changes from Open Firmware Working Group Meeting of 01/16/96.) 216 569.33 T 0.98 (Added new section \0506.2.2\051 describing physical address formats and representa-) 216 557.33 P (tions for CPU nodes.) 216 545.33 T (Applied proposal 291.) 216 533.33 T 0.52 (Changed the two notes in Section 12.2 to regular text since they both contained) 216 521.33 P (requirements.) 216 509.33 T 2 F (Revision 1.9) 72 485.33 T (Feb. 9,1996) 144 485.33 T 1 F 2.38 (Included changes from Open Firmware Working Group Binding Committee) 216 485.33 P 0.63 (Meeting review of Revision 1.7 on 01/17/96 and Proposal #306. Editor is now) 216 473.33 P (John Kingman.) 216 461.33 T 2 F (Revision 1.10) 72 437.33 T (Mar. 12,1996) 144 437.33 T 1 F 2.38 (Included changes from Open Firmware Working Group Binding Committee) 216 437.33 P (Meeting review of Revision 1.9 DRAFT on 03/05/96 and Proposal #317.) 216 425.33 T 0 0 0 1 0 0 0 K FMENDPAGE %%EndPage: "4" 4 %%Page: "5" 5 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (5) 72 750 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (PowerPC Processor binding) 435.49 750 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 0 1 0 0 0 K 1 12 Q 0 X (1) 36 711 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (2) 36 699 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (3) 36 687 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (4) 36 675 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (5) 36 663 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (6) 36 651 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (7) 36 639 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (8) 36 627 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (9) 36 615 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (10) 36 603 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (11) 36 591 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (12) 36 579 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (13) 36 567 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (14) 36 555 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (15) 36 543 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (16) 36 531 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (17) 36 519 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (18) 36 507 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (19) 36 495 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (20) 36 483 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (21) 36 471 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (22) 36 459 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (23) 36 447 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (24) 36 435 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (25) 36 423 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (26) 36 411 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (27) 36 399 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (28) 36 387 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (29) 36 375 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (30) 36 363 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (31) 36 351 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (32) 36 339 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (33) 36 327 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (34) 36 315 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (35) 36 303 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (36) 36 291 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (37) 36 279 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (38) 36 267 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (39) 36 255 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (40) 36 243 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (41) 36 231 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (42) 36 219 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (43) 36 207 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (44) 36 195 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (45) 36 183 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (46) 36 171 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (47) 36 159 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (48) 36 147 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (49) 36 135 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (50) 36 123 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (51) 36 111 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (52) 36 99 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (53) 36 87 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (54) 36 75 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (55) 36 63 T 0 0 0 1 0 0 0 K 27 72 54 720 C 0 0 612 792 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 2 18 Q 0 X 0 0 0 1 0 0 0 K (T) 72 708 T (able of Contents) 82.35 708 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 1 12 Q (1. Overview) 90 619 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 150 619 T ( 7) 459 619 T (2. References and Terms) 90 605 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 210 605 T ( 7) 459 605 T (2.1 References) 108 591 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 180 591 T (7) 462 591 T (2.2 Terms) 108 577 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 159 577 T (7) 462 577 T (3. Data Formats and Representations) 90 563 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 267 563 T ( 8) 459 563 T (4. Memory Management) 90 549 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 210 549 T ( 8) 459 549 T (4.1 PowerPC address translation model) 108 535 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . .) 297 535 T (8) 462 535 T (4.1.1 Translation requirements) 126 521 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 276 521 T (8) 462 521 T (4.1.2 Segmented Address Translation) 126 507 T ( . . . . . . . . . . . . . . . . . . . . . . . . .) 309 507 T (9) 462 507 T (4.1.3 Block Address Translation) 126 493 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 282 493 T (9) 462 493 T (4.2 Open Firmware\325s use of memory) 108 479 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 288 479 T (9) 462 479 T (4.2.1 Real-Mode) 126 465 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 207 465 T (10) 456 465 T (4.2.2 Virtual-Mode) 126 451 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 219 451 T (10) 456 451 T (4.2.3 Device Interface \050Real-Mode\051) 126 437 T ( . . . . . . . . . . . . . . . . . . . . . . . . .) 303 437 T (11) 456 437 T (4.2.4 Device Interface \050Virtual-Mode\051) 126 423 T (. . . . . . . . . . . . . . . . . . . . . . . .) 312 423 T (11) 456 423 T (4.2.5 Client Interface \050Real-Mode\051) 126 409 T (. . . . . . . . . . . . . . . . . . . . . . . . . . .) 294 409 T (11) 456 409 T (4.2.6 Client Interface \050Virtual-Mode\051) 126 395 T (. . . . . . . . . . . . . . . . . . . . . . . . .) 306 395 T (11) 456 395 T (4.2.7 User Interface \050Real-Mode\051) 126 381 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . .) 288 381 T (12) 456 381 T (4.2.8 User Interface \050Virtual-Mode\051) 126 367 T (. . . . . . . . . . . . . . . . . . . . . . . . . .) 300 367 T (12) 456 367 T (5. Properties) 90 353 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 153 353 T ( 13) 453 353 T (5.1 CPU properties) 108 339 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 201 339 T (13) 456 339 T (5.1.1 The Device Tree) 126 325 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 234 325 T (13) 456 325 T (5.1.2 Physical Address Formats and Representations for CPU Nodes) 126 311 T (13) 458.3 311 T (5.1.2.1 Numerical Representation) 144 297 T ( . . . . . . . . . . . . . . . . . . . . . . . .) 309 297 T (13) 456 297 T (5.1.2.2 Text Representation) 144 283 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 282 283 T (13) 456 283 T (5.1.2.3 Unit Address Representation) 144 269 T (. . . . . . . . . . . . . . . . . . . . . .) 324 269 T (13) 456 269 T (5.1.3 CPUS Node Properties) 126 255 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 264 255 T (13) 456 255 T (5.1.4 CPU Node Properties) 126 241 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 261 241 T (14) 456 241 T (5.1.5 TLB properties) 126 227 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 228 227 T (16) 456 227 T (5.1.6 Internal \050L1\051 cache properties) 126 213 T ( . . . . . . . . . . . . . . . . . . . . . . . . . .) 297 213 T (16) 456 213 T (5.1.7 Memory Management Unit properties) 126 199 T (. . . . . . . . . . . . . . . . . . . .) 336 199 T (17) 456 199 T (5.2 Ancillary \050L2,L3...\051 cache node properties) 108 185 T (. . . . . . . . . . . . . . . . . . . . .) 330 185 T (17) 456 185 T (6. Methods) 90 171 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 144 171 T ( 18) 453 171 T (6.1 MMU related methods) 108 157 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 237 157 T (18) 456 157 T (7. Client Interface Requirements) 90 143 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 249 143 T ( 18) 453 143 T (7.1 Calling Conventions) 108 129 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 228 129 T (18) 456 129 T (8. Client Program Requirements) 90 115 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 246 115 T ( 19) 453 115 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K FMENDPAGE %%EndPage: "5" 5 %%Page: "6" 6 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (6) 535.5 750 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 0 1 0 0 0 K 1 12 Q 0 X (1) 27 711 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (2) 27 699 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (3) 27 687 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (4) 27 675 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (5) 27 663 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (6) 27 651 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (7) 27 639 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (8) 27 627 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (9) 27 615 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (10) 27 603 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (11) 27 591 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (12) 27 579 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (13) 27 567 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (14) 27 555 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (15) 27 543 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (16) 27 531 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (17) 27 519 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (18) 27 507 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (19) 27 495 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (20) 27 483 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (21) 27 471 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (22) 27 459 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (23) 27 447 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (24) 27 435 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (25) 27 423 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (26) 27 411 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (27) 27 399 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (28) 27 387 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (29) 27 375 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (30) 27 363 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (31) 27 351 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (32) 27 339 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (33) 27 327 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (34) 27 315 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (35) 27 303 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (36) 27 291 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (37) 27 279 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (38) 27 267 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (39) 27 255 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (40) 27 243 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (41) 27 231 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (42) 27 219 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (43) 27 207 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (44) 27 195 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (45) 27 183 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (46) 27 171 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (47) 27 159 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (48) 27 147 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (49) 27 135 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (50) 27 123 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (51) 27 111 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (52) 27 99 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (53) 27 87 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (54) 27 75 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K (55) 27 63 T 0 0 0 1 0 0 0 K 0 0 612 792 C 0 0 0 1 0 0 0 K 1 12 Q 0 X 0 0 0 1 0 0 0 K (8.1 Load Address) 108 712 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 195 712 T (19) 456 712 T (8.2 Initial Program State) 108 698 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 228 698 T (20) 456 698 T (8.2.1 Initial Register Values) 126 684 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 261 684 T (20) 456 684 T (8.2.2 Initial Stack) 126 670 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 213 670 T (20) 456 670 T (8.2.3 Client Interface Handler Address) 126 656 T (. . . . . . . . . . . . . . . . . . . . . . . .) 312 656 T (21) 456 656 T (8.2.4 Client Program Arguments) 126 642 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 285 642 T (21) 456 642 T (8.3 Caching) 108 628 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 168 628 T (21) 456 628 T (8.4 Interrupts) 108 614 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 174 614 T (21) 456 614 T (8.5 Client callbacks) 108 600 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 204 600 T (21) 456 600 T (8.5.1 Real-Mode physical memory management assist callback) 126 586 T (. . . .) 432 586 T (22) 456 586 T (8.5.2 Virtual address translation assist callbacks) 126 572 T ( . . . . . . . . . . . . . . . .) 357 572 T (22) 456 572 T (9. User Interface Requirements) 90 558 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 240 558 T ( 22) 453 558 T (9.1 Machine Register Access) 108 544 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 249 544 T (23) 456 544 T (9.1.1 Branch Unit Registers) 126 530 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 261 530 T (23) 456 530 T (9.1.2 Fixed-Point Registers) 126 516 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 258 516 T (23) 456 516 T (9.1.3 Floating-Point Registers) 126 502 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 273 502 T (23) 456 502 T (10. Configuration Variables) 90 488 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 225 488 T ( 23) 453 488 T (11. MP Extensions) 90 474 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 183 474 T ( 24) 453 474 T (11.1 The Device Tree) 108 460 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 213 460 T (24) 456 460 T (11.1.1 Additional Properties) 126 446 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 264 446 T (24) 456 446 T (11.2 Initialization) 108 432 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 195 432 T (24) 456 432 T (11.3 Client Interface Services) 108 418 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 252 418 T (25) 456 418 T (11.4 Breakpoints) 108 404 T (. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 192 404 T (26) 456 404 T (11.5 Serialization) 108 390 T ( . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .) 195 390 T (27) 456 390 T 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K FMENDPAGE %%EndPage: "6" 6 %%Page: "7" 7 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (7) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 2 14 Q 0 X 0 0 0 1 0 0 0 K (1. Overview) 72 710.67 T 1 10 Q 1 (This document speci\336es the application of) 72 693.33 P 3 F 1 (IEEE Std 1275-1994 Standar) 249.65 693.33 P 1 (d for Boot \050Initialization, Con\336guration\051) 369.22 693.33 P 1 (Firmwar) 72 681.33 P 1 (e, Cor) 107.19 681.33 P 1 (e Practices and Requir) 132.82 681.33 P 1 (ements) 227.38 681.33 P 1 F 1 ( to computer systems that use the PowerPC Instruction Set) 255.15 681.33 P 0.86 (Architecture, including instruction-set-speci\336c requirements and practices for debugging, client program interface) 72 669.33 P 1 (and data formats. An implementation of Open Firmware for PowerPC) 72 657.33 P 3 F 1 (shall) 364.46 657.33 P 1 F 1 ( implement the core requirements as) 383.91 657.33 P 1 (de\336ned in [1] and the PowerPC-speci\336c extensions described in this binding.) 72 645.33 P 1 (While this document addresses the of) 72 626.33 P 1 (\336cial PowerPC architecture [2], the name "PowerPC" only requires) 226.52 626.33 P 1 (compliance to Book I. The descriptions that follow) 72 614.33 P 1 (, and the relevant sections describing translation features for) 282.22 614.33 P 1 (this binding, assume that the system\325) 72 602.33 P 1 (s PowerPC processor\050s\051 implement the entire set of Books I-III. Some) 224.23 602.33 P 1 ("PowerPC" processors may implement dif) 72 590.33 P 1 (ferent Book II-III features; such processors may need a variant of this) 245.08 590.33 P 1 (binding describing the dif) 72 578.33 P 1 (ferences to the mapping functions, etc.) 177.87 578.33 P 2 14 Q (2. Refer) 72 547.67 T (ences and T) 122.67 547.67 T (erms) 192.16 547.67 T (2.1. Refer) 72 515.67 T (ences) 133.17 515.67 T 1 10 Q 1 (This standard shall be used in conjunction with the following publications. When the following standards are) 72 498.33 P 1 (superseded by an approved revision, the revision) 72 486.33 P 3 F 1 (shall) 276.74 486.33 P 1 F 1 ( apply) 296.19 486.33 P 1 (.) 321.26 486.33 P ([1]) 72 467.33 T 3 F 1 (IEEE Std 1275-1994 Standar) 90 467.33 P 1 (d for Boot \050Initialization, Con\336guration\051 Firmwar) 209.57 467.33 P 1 (e, Cor) 414.78 467.33 P 1 (e Practices and) 440.41 467.33 P (Requir) 72 455.33 T (ements) 98.85 455.33 T 1 F (.) 126.62 455.33 T ([2]) 72 436.33 T 3 F 1 (PowerPC Ar) 90 436.33 P 1 (chitectur) 142.02 436.33 P 1 (e) 177.2 436.33 P 1 F 1 (, published by Mor) 181.64 436.33 P 1 (gan Kaufmann Publishers, Inc. \050ISBN 1-55960-316-6\051. Also) 260.57 436.33 P 1 (available from IBM \050Customer Reorder Number 52G7487\051. Updates to this document are available at) 72 424.33 P (http://www) 72 412.33 T (.austin.ibm.com/tech/ppc-chg.html) 116.91 412.33 T 2 14 Q (2.2. T) 72 381.67 T (erms) 108.05 381.67 T 1 10 Q 1 (This standard uses technical terms as they are de\336ned in the documents cited in \322References\323 on page) 72 364.33 P 1 (7, plus) 497.63 364.33 P 1 (the following terms:) 72 352.33 P 2 F 1 (cor) 72 333.33 P 1 (e, cor) 85.7 333.33 P 1 (e speci\336cation) 109.84 333.33 P 1 F 1 (: refers to) 170.56 333.33 P 3 F 1 (IEEE Std 1275-1994 Standar) 214.38 333.33 P 1 (d for Boot \050Initialization, Con\336guration\051) 333.95 333.33 P 1 (Firmwar) 72 321.33 P 1 (e, Cor) 107.19 321.33 P 1 (e Practices and Requir) 132.82 321.33 P 1 (ements) 227.38 321.33 P 2 F 1 (effective addr) 72 302.33 P 1 (ess) 131.41 302.33 P 1 F 1 (: The 64- or 32-bit address computed by the processor when executing a Storage Access or) 143.63 302.33 P 1 (Branch instruction, or when fetching the next sequential instruction. If address translation is disabled, the real) 72 290.33 P 1 (address is the same as the ef) 72 278.33 P 1 (fective address. If address translation is enabled, the real address is determined by) 190.57 278.33 P 1 (,) 533.12 278.33 P 1 (but not necessarily identical to, the ef) 72 266.33 P 1 (fective address.) 227.52 266.33 P 2 F 1 (linkage ar) 72 247.33 P 1 (ea) 115.88 247.33 P 1 F 1 (: An area within the stack that is reserved for saving certain registers across procedure calls in) 125.32 247.33 P 1 (PowerPC run-time models. This area is reserved by the caller and is allocated above the current stack pointer) 72 235.33 P (\050) 72 223.33 T 4 F (%r1) 75.33 223.33 T 1 F (\051.) 93.33 223.33 T 2 F 1 (Open Firmwar) 72 204.33 P 1 (e) 136.98 204.33 P 1 F 1 (: The \336rmware architecture de\336ned by the core speci\336cation or) 141.42 204.33 P 1 (, when used as an adjective, a) 401.9 204.33 P 1 (software component compliant with the core speci\336cation.) 72 192.33 P 2 F 1 (pr) 72 173.33 P 1 (ocedur) 81.82 173.33 P 1 (e descriptor) 111.08 173.33 P 1 F 1 (: a data structure used by some PowerPC run-time models to represent a C "pointer to) 162.9 173.33 P 1 (procedure". The \336rst word of this structure contains the actual address of the procedure.) 72 161.33 P 2 F 1 (r) 72 142.33 P 1 (eal addr) 76.26 142.33 P 1 (ess) 112.36 142.33 P 1 F 1 (: An address that the processor presents on the processor bus.) 124.58 142.33 P 2 F 1 (Real-Mode) 72 123.33 P 1 F 1 (: The mode in which all addresses passed between the client and Open Firmware are real addresses.) 119.21 123.33 P 2 F 1 (pr) 72 104.33 P 1 (ocessor bus) 81.82 104.33 P 1 F 1 (: The bus that connects the CPU chip to the system.) 131.43 104.33 P 52 409 54 419 R V 52 120 54 130 R V FMENDPAGE %%EndPage: "7" 7 %%Page: "8" 8 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (8) 535.5 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 2 10 Q 0 X 0 0 0 1 0 0 0 K 1 (segmented addr) 72 713.33 P 1 (ess translation) 140.87 713.33 P 1 F 1 (: The process whereby an Ef) 203.26 713.33 P 1 (fective Address \050EA\051 is translated into a V) 325.71 713.33 P 1 (irtual) 502.35 713.33 P 1 (Address \050V) 72 701.33 P 1 (A) 117.53 701.33 P 128.08 700.24 124.75 700.24 2 L V 0.49 H 0 Z N 1 (\051) 124.75 701.33 P 1 ( and the virtual address is translated into a Real Address \050RA\051. \050See \322Segmented Address) 128.08 701.33 P 1 (T) 72 689.33 P 1 (ranslation\323 on page) 77.76 689.33 P 1 (9. and Section 4.3 of Book III of [2] for more detail.\051) 160.02 689.33 P 2 F 1 (T) 72 670.33 P 1 (able of Contents \050T) 77.75 670.33 P 1 (OC\051) 162.51 670.33 P 1 F 1 (: A data structure used by some PowerPC run-time models that is used for access to) 180.84 670.33 P 1 (global variables and for inter) 72 658.33 P 1 (-module linkage. When a T) 191.33 658.33 P 1 (OC is used,) 304.85 658.33 P 2 F 1 (%r2) 356.74 658.33 P 1 F 1 ( contains its base address.) 376.18 658.33 P 2 F 1 (virtual addr) 72 639.33 P 1 (ess) 124.77 639.33 P 1 F 1 ( \050in IEEE 1275 parlance\051: the address that a program uses to access a memory location or) 136.99 639.33 P 1 (memory-mapped device register) 72 627.33 P 1 (. Depending on the presence or absence of memory mapping hardware in the) 202.86 627.33 P 1 (system, and whether or not that mapping hardware is enabled, a virtual address may or may not be the same as) 72 615.33 P 1 (the physical \050real\051 address that appears on an external bus. The IEEE 1275 de\336nition of "virtual address") 72 603.33 P 0.8 (corresponds to The PowerPC Architecture's de\336nition of "ef) 72 591.33 P 0.8 (fective addres." Except as noted, this document uses) 318.51 591.33 P 1 (the IEEE 1275 de\336nition of virtual address.) 72 579.33 P 2 F 1 (V) 72 560.33 P 1 (irtual Addr) 78.85 560.33 P 1 (ess) 128.84 560.33 P 1 F 1 (\050in PowerPC parlance\051: An internal address within the PowerPC address translation) 144.56 560.33 P 1 (mechanism, used as in intermediate term in the translation of an ef) 72 548.33 P 1 (fective address to the corresponding real) 348.89 548.33 P (address.) 72 536.33 T 2 F 1 (V) 72 517.33 P 1 (irtual-Mode) 78.85 517.33 P 1 F 1 (: The mode in which Open Firmware and its client share a single virtual address space, and) 130.51 517.33 P 0.85 (address translation is enabled; all addresses passed between the client and Open Firmware are virtual \050translated\051) 72 505.33 P (addresses.) 72 493.33 T 2 14 Q (3. Data Formats and Repr) 72 462.67 T (esentations) 231.95 462.67 T 1 10 Q 1 (The cell size) 72 445.33 P 3 F 1 (shall) 128.04 445.33 P 1 F 1 ( be 32 bits. Number ranges for) 147.49 445.33 P 3 F 1 (n) 278.91 445.33 P 1 F 1 (,) 283.91 445.33 P 3 F 1 (u) 289.91 445.33 P 1 F 1 (, and other cell-sized items are consistent with 32-bit,) 294.91 445.33 P 1 (two's-complement number representation.) 72 433.33 P 1 (The required alignment for items accessed with) 72 414.33 P 3 F 1 (a-addr) 271.46 414.33 P 1 F 1 ( addresses) 298.68 414.33 P 3 F 1 (shall) 344 414.33 P 1 F 1 ( be four) 363.45 414.33 P 1 (-byte aligned \050i.e., a multiple of) 396.35 414.33 P (4\051.) 72 402.33 T 1 (Each operation involving a) 72 383.33 P 3 F 1 (qaddr) 186.54 383.33 P 1 F 1 ( address) 210.43 383.33 P 3 F 1 (shall) 247.42 383.33 P 1 F 1 ( be performed with a single 32-bit access to the addressed) 266.87 383.33 P 1 (location; similarly) 72 371.33 P 1 (, each) 145.41 371.33 P 3 F 1 (waddr) 173.23 371.33 P 1 F 1 ( access) 198.79 371.33 P 3 F 1 (shall) 231.33 371.33 P 1 F 1 ( be performed with a single 16-bit access. This implies four) 250.78 371.33 P 1 (-byte) 498.6 371.33 P 1 (alignment for) 72 359.33 P 3 F 1 (qaddrs) 130.66 359.33 P 1 F 1 ( and two-byte alignment for) 158.44 359.33 P 3 F 1 (waddrs) 277.59 359.33 P 1 F 1 (.) 307.04 359.33 P 2 14 Q (4. Memory Management) 72 328.67 T (4.1. PowerPC addr) 72 296.67 T (ess translation model) 188.79 296.67 T 1 10 Q 1 (This section describes the model that is used for co-existence of Open Firmware and client programs \050i.e.,) 72 279.33 P 1 (operating systems\051 with respect to address translation.) 72 267.33 P 0.82 (The following overview of translation is provided so that the issues relevant to Open Firmware for PowerPC can) 72 248.33 P 1 (be discussed. Details that are not relevant to Open Firmware issues \050e.g., protection\051 are not described in detail;) 72 236.33 P 1 (the PowerPC architecture [2], particularly Book III, should be consulted for the details. For the scope of this) 72 224.33 P 1 (section, terms will be used as de\336ned in [2].) 72 212.33 P 2 12 Q (4.1.1. T) 72 187 T (ranslation r) 112.12 187 T (equir) 172.24 187 T (ements) 199.36 187 T 1 10 Q 2.26 (The default access mode of storage for load and stores \050i.e., with translation disabled -- referred to as) 72 170.33 P 3 F 2.26 (Real-) 518.34 170.33 P 1.23 (Mode) 72 158.33 P 1 F 1.23 (\051 within PowerPC assumes that caches are enabled \050in copy-back mode\051. In order to perform access to I/O) 94.77 158.33 P 1.23 (device registers, the access mode must be set to Cache-Inhibited, Guarded by establishing a translation with this) 72 146.33 P 1.24 (mode and enabling translation. Thus, even though most of a client program and/or Open Firmware can run with) 72 134.33 P 1 (translation disabled, it) 72 122.33 P 185.56 121.24 166.11 121.24 2 L V N 1 (must) 166.11 122.33 P 1 ( be enabled when performing I/O.) 185.56 122.33 P FMENDPAGE %%EndPage: "8" 8 %%Page: "9" 9 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (9) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 2 12 Q 0 X 0 0 0 1 0 0 0 K (4.1.2. Segmented Addr) 72 712 T (ess T) 191.11 712 T (ranslation) 215.89 712 T 2 9 Q 0.9 (Note: the use of the term V) 108 693 P 0.9 (irtual Addr) 216.53 693 P 0.9 (ess in this section r) 261.52 693 P 0.9 (efers to the PowerPC de\336nition,) 336.96 693 P 0.9 (while the r) 108 683 P 0.9 (est of the document uses the IEEE 1275 de\336nition of virtual addr) 150.63 683 P 0.9 (ess. \050See \322Ref-) 409.13 683 P 0.9 (er) 108 673 P 0.9 (ences and T) 115.83 673 P 0.9 (erms\323 on page) 162.31 673 P 0.9 (7.\051) 221.85 673 P 1 10 Q 1 (An Ef) 72 658.33 P 1 (fective Address \050EA\051 of a PowerPC processor is 64{32} bits wide. Each EA is translated into an 80{52}-) 96.98 658.33 P 1 (bit V) 72 646.33 P 1 (irtual Address \050V) 92.68 646.33 P 1 (A) 162.82 646.33 P 173.37 645.24 170.04 645.24 2 L V 0.49 H 0 Z N 1 (\051) 170.04 646.33 P 1 ( by prepending a 52{24}-bit V) 173.37 646.33 P 1 (irtual Segment Id \050VSID\051 to the 28 LSbs of the ef) 300.41 646.33 P 1 (fective) 508.54 646.33 P 0.88 (address. On 32-bit implementations, the VSID is obtained by indexing into a set of 16 Segment Registers \050SRs\051) 72 634.33 P 1 (using the 4 MSbs of the EA. On 64-bit implementations, the VSID is looked up in a Segment T) 72 622.33 P 1 (able using the) 470.96 622.33 P 1 (36 MSbs of the EA. Finally) 72 610.33 P 1 (, the virtual address is translated into a Real Address \050RA\051. This is done by) 186.91 610.33 P 1 (mapping the V) 72 598.33 P 1 (irtual Page-Number \050VPN\051 \050bits 0-67{39} of the V) 132.84 598.33 P 1 (A\051 into a Real Page Number \050RPN\051 and) 342.84 598.33 P 1 (concatenating this RPN with the byte of) 72 586.33 P 1 (fset \05012 LSbs of the V) 237.81 586.33 P 1 (A\051. The mapping of VPN to RPN involves a) 330.12 586.33 P 1 (hashing algorithm within a Hashed Page T) 72 574.33 P 1 (able \050HT) 247.84 574.33 P 1 (AB\051 to locate a Page T) 283.86 574.33 P 1 (able Entry \050PTE\051 that matches the) 379.53 574.33 P 1 (VPN and using that entry\325) 72 562.33 P 1 (s RPN component. If a valid entry is not found, a Data Storage Interrupt \050DSI\051 or) 180.44 562.33 P 1 (Instruction Storage Interrupt \050ISI\051 is signalled, depending upon the source of the access.) 72 550.33 P 1 (This process is not performed for every translation! Processors will typically have a T) 72 531.33 P 1 (ranslation Look-aside) 428.2 531.33 P 1 (Buf) 72 519.33 P 1 (fer \050TLB\051 that caches the most recent translations, thus exploiting the natural spatial locality of programs to) 86.82 519.33 P 1 (reduce the overhead of address translation. 64-bit implementations may also implement a Segment Lookaside) 72 507.33 P 1 (Buf) 72 495.33 P 1 (fer \050SLB\051 for the same reasons. On most PowerPC processors, the TLB updates are performed in hardware.) 86.82 495.33 P 1 (However) 72 483.33 P 1 (, the architecture allows an implementation to use a software-assisted mechanism to perform the TLB) 108.25 483.33 P 1 (updates. Such schemes must not af) 72 471.33 P 1 (fect the architected state of the processor unless the translation fails; i.e., the) 216.25 471.33 P 1 (HT) 72 459.33 P 1 (AB does not contain a valid PTE for the V) 84.53 459.33 P 1 (A and a DSI/ISI is signalled.) 262.5 459.33 P 2 9 Q 0.9 (Note: one unusual featur) 108 441 P 0.9 (e of this translation mechanism is that valid translations might) 205.79 441 P 0.9 (not be found in the HT) 108 431 P 0.9 (AB; the HT) 199.6 431 P 0.9 (AB might be too small to contain all of the curr) 245.74 431 P 0.9 (ently) 435.56 431 P 0.9 (valid translations. This intr) 108 421 P 0.9 (oduces a level of complexity in the use of addr) 215.56 421 P 0.9 (ess translation) 399.24 421 P 0.9 (by Open Firmwar) 108 411 P 0.9 (e, as discussed below) 179.14 411 P 0.9 (.) 260.85 411 P 2 12 Q (4.1.3. Block Addr) 72 387 T (ess T) 164.46 387 T (ranslation) 189.24 387 T 1 10 Q 0.81 (T) 72 370.33 P 0.81 (o further reduce the translation overhead for contiguous regions of virtual and real address spaces \050e.g., a frame) 77.41 370.33 P 1 (buf) 72 358.33 P 1 (fer) 85.15 358.33 P 1 (, or all of real memory\051, the Block Address T) 95.85 358.33 P 1 (ranslation \050BA) 285.3 358.33 P 1 (T\051 mechanism is also supported by PowerPC.) 344.35 358.33 P 1 (The Block Address T) 72 346.33 P 1 (ranslation involves the use of BA) 160.47 346.33 P 1 (T entries that contain a Block Ef) 297.96 346.33 P 1 (fective Page Index) 433.76 346.33 P 1 (\050BEPI\051, a Block Length \050BL\051 speci\336er and a Block Real Page Number \050BRPN\051; the architecture de\336nes 4 BA) 72 334.33 P 1 (T) 526.71 334.33 P 1 (entries for data \050DBA) 72 322.33 P 1 (T entries\051 and 4 BA) 160.81 322.33 P 1 (T entries for instruction \050IBA) 243.13 322.33 P 1 (T entries\051) 363.78 322.33 P 1 8 Q 0.8 (1) 403.38 326.33 P 1 10 Q 1 (. BA) 407.38 322.33 P 1 (T areas are restricted to a) 426.16 322.33 P 1 (\336nite set of allowable lengths, all of which are powers of 2. The smallest BA) 72 310.33 P 1 (T area de\336ned is 128 KB \0502) 395.57 310.33 P 1 8 Q 0.8 (17) 512.66 314.33 P 1 10 Q 1 (bytes\051. The lar) 72 298.33 P 1 (gest BA) 135.36 298.33 P 1 (T area de\336ned is 256 MB \0502) 167.75 298.33 P 1 8 Q 0.8 (28) 286.51 302.33 P 1 10 Q 1 ( bytes\051. The starting address of a BA) 294.51 298.33 P 1 (T area in both EA) 450.54 298.33 P 1 (space and RA space must be a multiple of the area's length.) 72 286.33 P 1 (Block Address T) 72 267.33 P 1 (ranslation is done my matching a number of upper bits of the EA \050speci\336ed by the BL value\051) 141.42 267.33 P 1 (against each of the BA) 72 255.33 P 1 (T entries. If a match is found, the corresponding BRPN bits replace the matched bits in) 165.98 255.33 P 1 (the EA to produce the RA.) 72 243.33 P 1 (Block Address T) 72 224.33 P 1 (ranslation takes precedence over Segmented Address T) 141.42 224.33 P 1 (ranslation; i.e., if a mapping for a) 368.12 224.33 P 0.9 (storage location is present in both a BA) 72 212.33 P 0.9 (T entry and a Page T) 235.22 212.33 P 0.9 (able Entry or HT) 322.6 212.33 P 0.9 (AB, the Block Address T) 392.54 212.33 P 0.9 (ranslation) 497.16 212.33 P 1 (will be used.) 72 200.33 P 2 14 Q (4.2. Open Firmwar) 72 169.67 T (e\325) 189.57 169.67 T (s use of memory) 199.93 169.67 T 1 10 Q 1 (Open Firmware shall use the memory resources within the space indicated by the) 72 152.33 P 4 F 2.4 (real-base, real-) 412.44 152.33 P 2.4 (size, virt-base) 72 140.33 P 5 F 2.4 (and) 172.8 140.33 P 4 F 2.4 ( virt-size) 190.8 140.33 P 1 F 1 ( Con\336guration V) 253.2 140.33 P 1 (ariables de\336ned for PowerPC. As described in the) 321.87 140.33 P 72 86 540 116 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 207 94 351 94 2 L 0.25 H 2 Z 0 X 0 0 0 1 0 0 0 K N 0 0 612 792 C 1 8 Q 0 X 0 0 0 1 0 0 0 K (1) 108 83.33 T 1 10 Q (The 601 has a single set of BA) 114 79.33 T (T entries that are shared by both instruction and data accesses.) 235.93 79.33 T 52 137 54 159 R V FMENDPAGE %%EndPage: "9" 9 %%Page: "10" 10 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (10) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 1 10 Q 0 X 0 0 0 1 0 0 0 K 1 (applicable platform binding, a mechanism is de\336ned to enable Open Firmware to determine if its current) 72 713.33 P 1 (con\336guration is consistent with the requirements of the client.) 72 701.33 P 1 (If the client program has speci\336c requirements for physical memory or address space usage, it may establish) 72 682.33 P 1 (requirements for Open Firmware's physical and/or virtual address space usage by means of its program header) 72 670.33 P 1 (.) 527.87 670.33 P 1 (When Open Firmware loads the client program, it inspects the program header) 72 658.33 P 1 (, and if its current usage of) 396.98 658.33 P 1 (physical memory or virtual address space con\337icts with that speci\336ed in the program header) 72 646.33 P 1 (, Open Firmware) 453.15 646.33 P 0.89 (shall set the) 72 634.33 P 2 F 0.89 (r) 124.39 634.33 P 0.89 (eal-base) 128.65 634.33 P 1 F 0.89 (,) 163.09 634.33 P 2 F 0.89 (r) 168.98 634.33 P 0.89 (eal-size) 173.24 634.33 P 1 F 0.89 (,) 204.34 634.33 P 2 F 0.89 (virt-base) 210.23 634.33 P 1 F 0.89 (, and) 248 634.33 P 2 F 0.89 (virt-size) 271.72 634.33 P 1 F 0.89 ( to the con\336guration variables as speci\336ed in the header) 306.15 634.33 P 1 (and restart itself.) 72 622.33 P 2 F 1 (Real-base) 147.93 622.33 P 1 F 1 (,) 189.59 622.33 P 2 F 1 (r) 195.59 622.33 P 1 (eal-size) 199.85 622.33 P 1 F 1 (,) 230.95 622.33 P 2 F 1 (virt-base) 236.95 622.33 P 1 F 1 (, and) 274.72 622.33 P 2 F 1 (virt-size) 298.66 622.33 P 1 F 1 ( may be speci\336ed as -1, in which case the) 333.09 622.33 P 1 (\336rmware is permitted to choose appropriate values for the variables speci\336ed as -1.) 72 610.33 P 1 (If the values of the) 72 591.33 P 2 F 1 (r) 154.48 591.33 P 1 (eal-size) 158.74 591.33 P 1 F 1 ( and/or) 189.84 591.33 P 2 F 1 (virt-size) 222.39 591.33 P 1 F 1 ( con\336guration variables do not provide suf) 256.82 591.33 P 1 (\336cient memory and/or) 432.62 591.33 P 1 (virtual address space for the \336rmware's own use, then the \336rmware shall not attempt to load a client program) 72 579.33 P 1 (and the condition should be reported to the user) 72 567.33 P 1 (. The possibility of not being able to comply with limitiations) 269.98 567.33 P 1 (on \336rmware's size should be tested as the \336rmware is coming up in order to handle the possibility that a user) 72 555.33 P 1 (established an unworkable limitation on the size. Clients can minimize this exposure by setting size to -1 and) 72 543.33 P 1 (allowing Open Firmware to choose the size.) 72 531.33 P 1 (A PowerPC Open Firmware binding) 72 512.33 P 3 F 1 (shall) 225.6 512.33 P 1 F 1 ( support two dif) 245.05 512.33 P 1 (ferent addressing models, depending upon the setting) 311.48 512.33 P 1 (of the) 72 500.33 P 4 F 2.4 (real-mode?) 99.55 500.33 P 1 F 1 ( Con\336guration V) 159.55 500.33 P 1 (ariable. This variable indicates the Open Firmware addressing mode that a) 228.22 500.33 P 1 (client program expects;) 72 488.33 P 4 F 2.4 (false) 171.37 488.33 P 1 F 1 ( \0500\051 indicates V) 201.37 488.33 P 1 (irtual-Mode,) 265.7 488.33 P 4 F 2.4 (true) 319.47 488.33 P 1 F 1 ( \050-1\051 indicates Real-Mode; the default value of) 343.47 488.33 P 4 F 2.4 (real-mode?) 72 476.33 P 1 F 1 ( is implementation dependent.) 132 476.33 P 1.19 (The management of) 72 457.33 P 4 F 2.87 (real-mode?) 158.06 457.33 P 1 F 1.19 ( is analogous to) 218.06 457.33 P 4 F 2.87 (little-endian?) 287.84 457.33 P 1 F 1.19 (. Open Firmware determines its address-) 371.84 457.33 P 1.63 (ing mode using the value of) 72 445.33 P 4 F 3.92 (real-mode?) 195.69 445.33 P 1 F 1.63 (. If the current state of) 255.69 445.33 P 4 F 3.92 (real-mode?) 356.86 445.33 P 1 F 1.63 ( \050and hence, the current state) 416.86 445.33 P 1.74 (of Open Firmware\051 is incorrect, it) 72 433.33 P 3 F 1.74 (shall) 219.91 433.33 P 1 F 1.74 ( set) 239.36 433.33 P 4 F 4.18 (real-mode?) 258.95 433.33 P 1 F 1.74 ( appropriately and reset itself, possibly by executing) 318.95 433.33 P 4 F (reset-all) 72 421.33 T 1 F (.) 126 421.33 T 1 (Memory that cannot be allocated for general purpose use, for example physical memory on PowerPC systems) 72 404.33 P 1 (used for interrupt vectors and implementation speci\336c areas, shall not appear in the ") 72 392.33 P 5 F 2.4 (available) 424.02 392.33 P 1 F 1 (" property of) 478.02 392.33 P 1 (the memory node. A Client Program that needs to use such memory for its architected purpose must not claim) 72 380.33 P 1 (that area prior to use.) 72 368.33 P 1 (In the following two sections, some of conventions in Real-Mode and V) 72 349.33 P 1 (irtual-Mode address translations are) 371.26 349.33 P 1 (described. Remaining sections describe the assumptions that Open Firmware makes about the state and control) 72 337.33 P 1 (of the system in regard to Open Firmware\325) 72 325.33 P 1 (s use of system resources for three Open Firmware interfaces \050e.g.) 249.25 325.33 P 1 (Device, User and Client interfaces\051.) 72 313.33 P 2 12 Q (4.2.1. Real-Mode) 72 288 T 1 10 Q 1.66 (In Real-Mode \050when) 72 271.33 P 4 F 3.98 (real-mode?) 162.79 271.33 P 1 F 1.66 ( is) 222.79 271.33 P 4 F 3.98 (true) 237.78 271.33 P 1 F 1.66 (\051, the use of address translations by Open Firmware and its client) 261.78 271.33 P 1.28 (are independent. Either they do not use translation, or their translations are private; they do not share any trans-) 72 259.33 P 2.39 (lations. All interfaces between the two must pass the real address of the data. Any data structure shared by) 72 247.33 P 1 (Open Firmware and its client that refers to) 72 235.33 P 3 F 1 (virt) 252.19 235.33 P 1 F 1 ( addresses in [1], or this binding, must be real addresses.) 266.08 235.33 P 2 9 Q 0.9 (Note: in particular) 108 217 P 0.9 (, that the addr) 180.96 217 P 0.9 (ess of the Client interface handler) 238.5 217 P 0.9 (, that is passed to the) 371.4 217 P 0.9 (client, has to be a r) 108 207 P 0.9 (eal addr) 184.83 207 P 0.9 (ess.) 217.32 207 P 1 10 Q 1 (The Con\336guration V) 72 192.33 P 1 (ariables) 156.22 192.33 P 4 F 2.4 (real-base) 190.82 192.33 P 1 F 1 ( and) 244.82 192.33 P 4 F 2.4 (real-size) 266.26 192.33 P 1 F 1 ( should indicate the physical memory base and size) 320.26 192.33 P 1 (in which Open Firmware must locate itself. In Real-Mode, the Con\336guration V) 72 180.33 P 1 (ariables) 405.8 180.33 P 4 F 2.4 (virt-base) 440.4 180.33 P 5 F 2.4 (and) 502.8 180.33 P 4 F 2.4 (virt-size) 72 168.33 P 1 F 1 ( do not have meaning and should be set to -1.) 126 168.33 P 2 12 Q (4.2.2. V) 72 143 T (irtual-Mode) 113.22 143 T 1 10 Q 1.56 (When) 72 126.33 P 4 F 3.75 (real-mode?) 99.94 126.33 P 1 F 1.56 ( is) 159.94 126.33 P 4 F 3.75 (false) 174.74 126.33 P 1 F 1.56 (, Open Firmware) 204.74 126.33 P 3 F 1.56 (shall) 279.97 126.33 P 1 F 1.56 ( con\336gure itself to run in) 299.42 126.33 P 3 F 1.56 (V) 410.45 126.33 P 1.56 (irtual-Mode) 415.82 126.33 P 1 F 1.56 (. In V) 464.15 126.33 P 1.56 (irtual-Mode,) 489.73 126.33 P 1.26 (Open Firmware and its client will share a single virtual address space. This binding provides interfaces to allow) 72 114.33 P 1 (Open Firmware and its client to ensure that this single virtual address model can be maintained.) 72 102.33 P 52 528 54 689 R V 52 389 54 399 R V 52 165 54 199 R V FMENDPAGE %%EndPage: "10" 10 %%Page: "11" 11 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (11) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 1 10 Q 0 X 0 0 0 1 0 0 0 K 1 (The Con\336guration V) 72 713.33 P 1 (ariables) 156.22 713.33 P 4 F 2.4 (virt-base) 190.82 713.33 P 5 F 2.4 (and) 253.22 713.33 P 4 F 2.4 ( virt-size) 271.22 713.33 P 1 F 1 ( should indicate the virtual address space base) 333.62 713.33 P 1 (address and size that Open Firmware should use. The Con\336guration V) 72 701.33 P 1 (ariables) 362.24 701.33 P 4 F 2.4 (real-base) 396.84 701.33 P 1 F 1 ( and) 450.84 701.33 P 4 F 2.4 (real-size) 472.28 701.33 P 1 F 1 (should indicate the physical memory base and size in which Open Firmware must locate itself.) 72 689.33 P 2 12 Q (4.2.3. Device Interface \050Real-Mode\051) 72 664 T 1 10 Q 1 (While Open Firmware is performing system initialization and probing functions, it establishes and maintains its) 72 647.33 P 1 (own translations. In particular) 72 635.33 P 1 (, it maintains its own Page T) 194.58 635.33 P 1 (ables \050and/or BA) 314.05 635.33 P 1 (T entries\051 and handles any DSI/ISI) 383.26 635.33 P 1 (interrupts itself.) 72 623.33 P 2 9 Q 0.9 (Note: in Real-Mode, all translations will be) 108 605 P 0 F 0.9 (virt=real) 281.3 605 P 2 F 0.9 (; the primary r) 313.42 605 P 0.9 (eason for translation is) 373.7 605 P 0.9 (to allow appr) 108 595 P 0.9 (opriate I/O accesses.) 160.64 595 P 2 12 Q (4.2.4. Device Interface \050V) 72 571 T (irtual-Mode\051) 203.84 571 T 1 10 Q 1.59 (Open Firmware will establish its own translation environment, handling DSI/ISI interrupts as in the Real-Mode) 72 554.33 P 2.17 (case. However) 72 542.33 P 2.17 (, this environment will, in general, contain translations in which virtual addresses do not equal) 132.63 542.33 P 1 (real addresses. The virtual address space used by Open Firmware must be compatible with its client.) 72 530.33 P 2 9 Q 0.9 (Note: Since these virtual addr) 108 512 P 0.9 (esses will be used by the Client and/or User Interfaces \050e.g.,) 225.93 512 P 0.9 (for pointers to its code, device-tr) 108 502 P 0.9 (ee, etc.\051, their translations must be pr) 236.81 502 P 0.9 (eserved until the cli-) 385.27 502 P 0.9 (ent OS decides that it no longer r) 108 492 P 0.9 (equir) 240.88 492 P 0.9 (es the services of Open Firmwar) 261.23 492 P 0.9 (e.) 389.29 492 P 2 12 Q (4.2.5. Client Interface \050Real-Mode\051) 72 468 T 1 10 Q 1.47 (In Real-Mode, addresses of client data are real.; the client must ensure that all data areas referred to across the) 72 451.33 P 1.25 (Client Interface are valid real addresses. This may require moving data to meet any requirements for contiguous) 72 439.33 P 2.77 (storage areas \050e.g., for) 72 427.33 P 4 F 6.64 (read/write) 174.42 427.33 P 1 F 2.77 ( calls\051. T) 234.42 427.33 P 2.77 (ranslation) 274.87 427.33 P 3 F 2.77 (shall) 319.58 427.33 P 1 F 2.77 ( be disabled before the client interface call is) 339.03 427.33 P (made.) 72 415.33 T 1 (Open Firmware will typically have to maintain its translations in order to perform I/O. Since the client may be) 72 398.33 P 1 (running with translation enabled \050except for the Client interface call\051, Open Firmware) 72 386.33 P 3 F 1 (shall) 429.76 386.33 P 1 F 1 ( save the state of all) 449.21 386.33 P 1 (relevant translation resources \050e.g., SDR1, BA) 72 374.33 P 1 (T) 261.69 374.33 P 1 (s\051 and restore them before returning to the client. Likewise, it) 267.1 374.33 P 3 F 1 (may) 72 362.33 P 1 F 1 ( take over interrupts for its own use \050e.g., for doing "lazy" allocation of BA) 88.66 362.33 P 1 (T) 402.16 362.33 P 1 (s\051; it) 407.57 362.33 P 3 F 1 (shall) 430.13 362.33 P 1 F 1 ( preserve the state of) 449.58 362.33 P 1 (any interrupt vectors for its client.) 72 350.33 P 1 (Since the state of the address translation system is not predictable to any interrupts, the client) 72 331.33 P 3 F 1 (shall) 462.68 331.33 P 1 F 1 ( ensure that) 482.13 331.33 P 1 (interrupts are disabled before calling the Client Interface handler and call the handler from only one CPU at a) 72 319.33 P 1 (time. The client) 72 307.33 P 3 F 1 (shall) 140.55 307.33 P 1 F 1 ( also ensure that other processors do not generate translation exceptions for the duration of) 160 307.33 P 1 (the call.) 72 295.33 P 0.98 (Client programs are not required to assume responsibility for physical memory management. The client program) 72 276.33 P 1 (must use the Open Firmware claim client interface service to allocate physical memory while physical memory) 72 264.33 P 1 (is managed by Open Firmware. Physical memory shall remain managed by Open Firmware until the client) 72 252.33 P 1 (program de\336nes the real-mode physical memory management assist callbacks. Physical memory must be) 72 240.33 P 1 (managed by the client program once the client program de\336nes the real-mode physical memory management) 72 228.33 P 1 (assist callbacks. Open Firmware shall use the client program's real-mode physical memory management assist) 72 216.33 P 1 (callbacks to allocate physical memory after the client program has assumed physical memory management.) 72 204.33 P 1 (In Real-Mode,) 72 185.33 P 2 F 1 (claim) 134.82 185.33 P 1 F 1 ( methods) 158.15 185.33 P 3 F 1 (shall) 199.04 185.33 P 1 F 1 ( not allocate more pages than are necessary to satisfy the request.) 218.49 185.33 P 2 12 Q (4.2.6. Client Interface \050V) 72 160 T (irtual-Mode\051) 201.19 160 T 1 10 Q 1 (Client interface calls are essentially "subroutine" calls to Open Firmware. Hence, the client interface executes in) 72 143.33 P 1 (the environment of its client, including any translations that the OS has established. E.g., addresses passed in to) 72 131.33 P 1 (the client interface are assumed to be valid virtual addresses within the scope of the OS. Any DSI/ISI interrupts) 72 119.33 P 1 (are either invalid addresses or caused by HT) 72 107.33 P 1 (AB "spills". In either case, the OS has the responsibility for the) 255.65 107.33 P 1 (handling of such exceptions.) 72 95.33 P 52 698 54 720 R V 52 201 54 314 R V FMENDPAGE %%EndPage: "11" 11 %%Page: "12" 12 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (12) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 2 9 Q 0 X 0 0 0 1 0 0 0 K 0.9 (Note: addr) 108 714 P 0.9 (esses that the Open Firmwar) 150.48 714 P 0.9 (e internal use will be those that wer) 264.4 714 P 0.9 (e established) 406.28 714 P 0.9 (by the Device interface \050or) 108 704 P 0.9 (, by subsequent actions of the Client or User interface\051. Thus,) 212.24 704 P 0.9 (the client must pr) 108 694 P 0.9 (eserve these Open Firmwar) 178.28 694 P 0.9 (e translations if it takes over the virtual) 286.54 694 P 0.9 (memory management function.) 108 684 P 1 10 Q 0.94 (In addition to using existing translations, the Client Interface might require the establishment of new translations) 72 669.33 P 1 (\050e.g., due to) 72 657.33 P 4 F 2.4 (map-in) 124.99 657.33 P 1 F 1 ( calls during) 160.99 657.33 P 4 F 2.4 (open) 215.93 657.33 P 1 F 1 ( time\051, or the removal of old translations \050e.g., during) 239.93 657.33 P 4 F 2.4 (map-out) 465.46 657.33 P 1 F 1 ( calls) 507.46 657.33 P 1 (during) 72 645.33 P 4 F 2.4 (close) 101.61 645.33 P 1 F 1 ( time\051. Since this requires altering the Client\325) 131.61 645.33 P 1 (s translation resources \050e.g., Page T) 318.6 645.33 P 1 (ables\051, possibly) 465.09 645.33 P 1 (handling spill conditions, Open Firmware can not know how to perform these updates.) 72 633.33 P 1 (Hence, there) 72 614.33 P 3 F 1 (shall) 127.03 614.33 P 1 F 1 ( be) 146.48 614.33 P 5 F 2.4 (callback) 162.92 614.33 P 1 F 1 ( services provided by the client for use by Open Firmware for such actions;) 210.92 614.33 P 1 (see section) 72 602.33 P 1 (8.5.2.) 119.1 602.33 P 1 (In order to let clients \050i.e., tar) 72 583.33 P 1 (get operating systems\051 know where Open Firmware lives in the address space, the) 194.74 583.33 P 1 (following rules) 72 571.33 P 3 F 1 (shall) 137.33 571.33 P 1 F 1 ( be followed by an Open Firmware implementation for PowerPC and by client programs.) 156.78 571.33 P 1 (Open Firmware:) 72 552.33 P 4 11 Q (\245) 108 533.33 T 1 10 Q (Open Firmware) 114.6 533.33 T 3 F (shall) 180.14 533.33 T 1 F ( maintain its "translations" "mmu"-node property \050see section) 199.59 533.33 T (5.1.7.\051) 448.11 533.33 T 4 11 Q (\245) 108 518.33 T 1 10 Q (Open Firmware\325) 114.6 518.33 T (s) 180.42 518.33 T 2 F (claim) 186.81 518.33 T 1 F ( methods) 210.14 518.33 T 3 F (shall) 249.03 518.33 T 1 F (not allocate more pages than are necessary to satisfy the) 270.98 518.33 T (request.) 117 506.33 T 4 11 Q -0.81 (\245) 108 491.33 P 1 10 Q -0.31 (When a client executes) 114.6 491.33 P 2 F -0.31 (set-callback) 208.34 491.33 P 1 F -0.31 (, Open Firmware) 258.89 491.33 P 3 F -0.31 (shall) 328.52 491.33 P 1 F -0.31 ( attempt to invoke the "translate" callback.) 347.96 491.33 P (If the translate callback is implemented, Open Firmware) 117 479.33 T 3 F (shall) 345.01 479.33 T 1 F ( cease use of address translation hard-) 364.46 479.33 T (ware, instead using the client callbacks for changes to address translation.) 117 467.33 T 1 (The) 117 452.33 P 2 F 1 (exit) 136.05 452.33 P 1 F 1 ( service must continue to work after a) 151.6 452.33 P 2 F 1 (set-callback) 312.9 452.33 P 1 F 1 ( that takes over address translation. This) 363.45 452.33 P 1 (implies that Open Firmware takes responsibility for address translation hardware upon) 117 440.33 P 2 F 1 (exit) 476.56 440.33 P 1 F 1 ( and must) 492.11 440.33 P 1 (maintain internal information about translations that it requests of the client.) 117 428.33 P 1 (Client Programs:) 72 409.33 P 4 11 Q -0.92 (\245) 108 390.33 P 1 10 Q -0.35 (Client programs that take control of the management of address translation hardware and expect to be) 114.6 390.33 P (able to subsequently invoke Open Firmware client services must provide callbacks to assist Open) 117 378.33 T (Firmware in address translation \050see section) 117 366.33 T (8.5.2.\051.) 295.3 366.33 T 4 11 Q (\245) 108 351.33 T 1 10 Q (A client program shall not directly manipulate any address translation hardware before it either a\051) 114.6 351.33 T (ceases to invoke OF client services or b\051 issues a) 117 339.33 T 2 F (set-callback) 314.74 339.33 T 1 F (to install the "translate" callback.) 367.79 339.33 T 2 9 Q 0.9 (Note: The intended sequence is that a client pr) 108 321 P 0.9 (ogram will \336rst issue a set-callback and) 293.03 321 P 0.9 (then take contr) 108 311 P 0.9 (ol of addr) 168.13 311 P 0.9 (ess translation hardwar) 207.27 311 P 0.9 (e. Addr) 299.91 311 P 0.9 (ess translation hardwar) 329.64 311 P 0.9 (e includes) 422.28 311 P 0.9 (BA) 108 301 P 0.9 (T entries, page table, segment r) 119.83 301 P 0.9 (egisters, Machine State Register and the interrupt vec-) 244.4 301 P 0.9 (tors r) 108 291 P 0.9 (elating to translation faults.) 129.98 291 P 2 12 Q (4.2.7. User Interface \050Real-Mode\051) 72 267 T 1 10 Q 1.29 (In Real-Mode, Open Firmware regains total control of the system. As with the Client interface in Real-Mode, it) 72 250.33 P 2.56 (should save the state of the translation resources \050including interrupt vectors\051 upon entry and should restore) 72 238.33 P 1 (them upon exit.) 72 226.33 P 2 12 Q (4.2.8. User Interface \050V) 72 201 T (irtual-Mode\051) 193.85 201 T 1 10 Q 1 (When the User interface is invoked, Open Firmware is responsible for managing the machine. Therefore, it will) 72 184.33 P 1 (take over control of any relevant interrupt vectors for its own handling. In particular) 72 172.33 P 1 (, it will take over DSI/ISI) 420.64 172.33 P 1 (handling in order to report errors to the user for bad addresses, protection violations, etc. However) 72 160.33 P 1 (, as described) 479.85 160.33 P 1 (above, one source of DSI/ISI may simply be HT) 72 148.33 P 1 (AB spills. As with the case of) 272.78 148.33 P 4 F 2.4 (map-in) 401.44 148.33 P 1 F 1 ( and) 437.44 148.33 P 4 F 2.4 (map-out) 458.88 148.33 P 1 F 1 ( calls,) 500.88 148.33 P 1 (the User interface can not know how to handle such spill conditions, itself, or even if this is, in fact, a spill) 72 136.33 P 1 (versus a bad address.) 72 124.33 P 1 (Hence, this binding de\336nes) 72 105.33 P 5 F 2.4 (callback) 187.38 105.33 P 1 F 1 ( services that the client provides for use by Open Firmware; see) 235.38 105.33 P (section) 72 93.33 T (8.5.2.) 102.83 93.33 T 127.83 92.24 125.33 92.24 2 L V 0.49 H 0 Z N (.) 125.33 93.33 T 52 145 54 155 R V 52 102 54 112 R V FMENDPAGE %%EndPage: "12" 12 %%Page: "13" 13 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (13) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 2 14 Q 0 X 0 0 0 1 0 0 0 K (5. Pr) 72 710.67 T (operties) 104.02 710.67 T 1 10 Q 1 (This section describes the standard properties of a PowerPC Open Firmware implementation.) 72 693.33 P 2 14 Q (5.1. CPU pr) 72 662.67 T (operties) 146.02 662.67 T 2 12 Q (5.1.1. The Device T) 72 636 T (r) 172.1 636 T (ee) 177.22 636 T 1 10 Q 0.97 (Open Firmware requires that the multiple instances of any device that appears more than once in the device tree) 72 619.33 P 1 (must be distinguishable by means of their \322reg\323 properties. The \322reg\323 property must express the \322address\323 of) 72 607.33 P 1 (each node relative to its parent \322bus\323. Furthermore, the core speci\336cation says that the root node of the device) 72 595.33 P 0.91 (tree usually represents the \322main physical bus\323 of the system. Thus, if processors are not directly addressable on) 72 583.33 P 1 (the main physical bus, as is expected to be the case on many/most PowerPC-based systems, the CPU nodes on) 72 571.33 P 0.91 (such systems may not be children of the root node but must instead be children of a pseudo-device node. In this) 72 559.33 P 1 (case, the name of the pseudo-device node, which will usually be a child of the root node, shall be \322cpus\323.) 72 547.33 P 1 (The \322cpus\323 node shall have one child node of device_type \322cpu\323 for each processor) 72 528.33 P 1 (.) 419.07 528.33 P 2 12 Q (5.1.2. Physical Addr) 72 503 T (ess Formats and Repr) 180.79 503 T (esentations for CPU Nodes) 292.9 503 T (5.1.2.1. Numerical Repr) 72 477 T (esentation) 196.76 477 T 1 10 Q 1 (The numerical representation of a processor) 72 460.33 P 1 (\325) 253.15 460.33 P 1 (s "address" in a PowerPC system shall consist of one cell, encoded) 255.93 460.33 P 1 (as follows \050Bit# 0 refers to the least signi\336cant bit\051:) 72 448.33 P 5 F (Bit#) 198 429.33 T (33222222 22221111 11111100 00000000) 225 429.33 T (10987654 32109876 54321098 76543210) 225 418.33 T (phys.lo cell:) 117 396.33 T (00000000 00000000 00000000 pppppppp) 225 396.33 T 1 F (where:) 90 371.33 T 5 F (pppppppp) 117 352.33 T -0.86 (is an 8-bit integer representing the interprocessor inter-) 198 352.33 P (rupt identifier used by the platform.) 198 341.33 T 2 12 Q (5.1.2.2. T) 72 307 T (ext Repr) 120.9 307 T (esentation) 165 307 T 1 10 Q 1 (The text representation of a processor) 72 290.33 P 1 (\325) 228.16 290.33 P 1 (s "address" shall be an ASCII hexadecimal number in the range) 230.94 290.33 P 5 F 2.4 (0...FF) 498.66 290.33 P 1 F 1 (.) 533.86 290.33 P 1 (Conversion of the hexadecimal number from text representation to numeric representation shall be case) 72 271.33 P 1 (insensitive, and leading zeros shall be permitted but not required.) 72 259.33 P 0.92 (Conversion from numeric representation to text representation shall use the lower case forms of the hexadecimal) 72 240.33 P 1 (digits in the range) 72 228.33 P 5 F 2.4 (a..f) 150.44 228.33 P 1 F 1 (, suppressing leading zeros.) 174.44 228.33 P 2 12 Q (5.1.2.3. Unit Addr) 72 203 T (ess Repr) 166.79 203 T (esentation) 210.23 203 T 1 10 Q 1 (A processor) 72 186.33 P 1 (\325) 121.41 186.33 P 1 (s "unit-number" \050i.e. the \336rst component of its ") 124.19 186.33 P 4 F 2.4 (reg) 323.31 186.33 P 1 F 1 (" value\051 is the interprocessor interrupt) 341.31 186.33 P 1 (destination identi\336er used by the platform. For a uni-processor platform, the "unit-number" shall be zero.) 72 174.33 P 2 12 Q (5.1.3. CPUS Node Pr) 72 149 T (operties) 181.44 149 T 1 10 Q 1 (The following properties shall be created within the "cpus" node.) 72 132.33 P 4 F ("#address-cells") 72 115.33 T 1 F 0.89 (Standard) 90 100.33 P 3 F 0.89 (pr) 128.94 100.33 P 0.89 (op-name) 137.46 100.33 P 1 F 0.89 ( to de\336ne the number of cells required to represent the physical addresses for the ") 172.45 100.33 P 5 F 2.14 (cpu) 514.53 100.33 P 1 F 0.89 (") 532.53 100.33 P 1 (nodes \050i.e., the children of the ") 90 90.33 P 5 F 2.4 (cpus) 222 90.33 P 1 F 1 (" node\051.) 246 90.33 P 52 525 54 535 R V 52 183 54 193 R V FMENDPAGE %%EndPage: "13" 13 %%Page: "14" 14 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (14) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 3 10 Q 0 X 0 0 0 1 0 0 0 K 1 (pr) 90 713.33 P 1 (op-encoded-array) 98.52 713.33 P 1 F 1 (: Integer constant 1, encoded as with) 170.72 713.33 P 4 F 2.4 (encode-int) 326.58 713.33 P 1 F 1 (.) 386.58 713.33 P 1 (The value of) 90 695.33 P 5 F 2.4 ("#address-cells") 146.04 695.33 P 1 F 1 ( for the "cpus" node) 242.04 695.33 P 3 F 1 (shall) 329.35 695.33 P 1 F 1 ( be) 348.8 695.33 P 5 F 2.4 (1) 365.24 695.33 P 1 F 1 (.) 371.24 695.33 P 4 F ("#size-cells") 72 677.33 T 1 F 1 (Standard) 90 662.33 P 3 F 1 (pr) 129.05 662.33 P 1 (op-name) 137.57 662.33 P 1 F 1 (to de\336ne the number of cells necessary to represent the length of a physical address) 176.06 662.33 P (range.) 90 652.33 T 3 F 1 (pr) 90 634.33 P 1 (op-encoded-array) 98.52 634.33 P 1 F 1 (: Integer constant 0, encoded as with) 170.72 634.33 P 2 F 1 (encode-int.) 326.58 634.33 P 1 F 1 (The value of ") 90 616.33 P 5 F 2.4 (#size-cells) 150.12 616.33 P 1 F 1 (" for the "cpus" pseudo-device node is 0 because the processors that are) 216.12 616.33 P 1 (represented by the cpu nodes do not consume any physical address space.) 90 606.33 P 2 12 Q (5.1.4. CPU Node Pr) 72 583 T (operties) 177.77 583 T 1 10 Q 1 (For each CPU in the system, a cpu-node) 72 566.33 P 3 F 1 (shall) 243.59 566.33 P 1 F 1 ( be de\336ned as a child of) 263.04 566.33 P 5 F 2.4 ("cpus.") 367.52 566.33 P 1 F 1 ( The following properties) 409.52 566.33 P 1 (apply to each of these nodes. The ") 72 554.33 P 5 F 2.4 (cpus) 219.16 554.33 P 1 F 1 (" node shall not have ") 243.16 554.33 P 5 F 2.4 (reg) 338.81 554.33 P 1 F 1 (" or ") 356.81 554.33 P 5 F 2.4 (ranges) 380.3 554.33 P 1 F 1 (" properties.) 416.3 554.33 P 4 F ("name") 72 535.33 T 1 F 1 (Open Firmware standard property) 90 520.33 P 1 (. The value of the is property shall be of the form: "PowerPC,",) 228.15 520.33 P 1 (where is the name of the processor chip which may be displayed to the user) 90 510.33 P 1 (.) 442.05 510.33 P 4 F 2.4 ("device_type") 72 492.33 P 1 F 1 (Open Firmware standard property) 90 477.33 P 1 (. The value of this property for CPU nodes) 228.15 477.33 P 3 F 1 (shall) 410.46 477.33 P 1 F 1 ( be) 429.91 477.33 P 5 F 2.4 ("cpu") 446.35 477.33 P 1 F 1 (.) 476.35 477.33 P 4 F ("reg") 72 459.33 T 1 F 1 (Standard) 90 444.33 P 3 F 1 (pr) 129.05 444.33 P 1 (op-name) 137.57 444.33 P 1 F 1 (to de\336ne a cpu node\325) 176.06 444.33 P 1 (s unit-address.) 263.38 444.33 P 3 F 1 (pr) 90 426.33 P 1 (op-encoded-array) 98.52 426.33 P 1 F 1 (: an integer encoded as with) 170.72 426.33 P 2 F 1 (encode-int) 291.14 426.33 P 1 F 1 (.) 335.58 426.33 P 1 (For a cpu node, the \336rst and only value of the "reg" property shall be the number of the per) 90 408.33 P 1 (-processor) 472.45 408.33 P 1 (interrupt line assigned to the processor represented by the node. For a uni-processor platform, the value of) 90 398.33 P 1 (the "reg" property shall be zero.) 90 388.33 P 4 F ("cpu-version") 72 370.33 T 1 F 1 (Standard property) 90 355.33 P 1 (, encoded as with) 162.28 355.33 P 4 F 2.4 (encode-int) 238.21 355.33 P 1 F 1 (, that represents the processor type. This shall be the) 298.21 355.33 P 1 (value obtained by reading the Processor V) 90 345.33 P 1 (ersion Register of the CPU.) 264.3 345.33 P 4 F ("clock-frequency") 72 327.33 T 1 F 1 (Standard property) 90 312.33 P 1 (, encoded as with) 162.28 312.33 P 4 F 2.4 (encode-int) 238.21 312.33 P 1 F 1 (, that represents the internal processor speed \050in hertz\051 of) 298.21 312.33 P 1 (this node.) 90 302.33 P 4 F ("timebase-frequency") 72 284.33 T 1 F 1 (Standard property) 90 269.33 P 1 (, encoded as with) 162.28 269.33 P 4 F 2.4 (encode-int) 238.21 269.33 P 1 F 1 (, that represents the rate \050in hertz\051 at which the PowerPC) 298.21 269.33 P 1 (T) 90 259.33 P 1 (imeBase and Decrementer registers are updated.) 95.76 259.33 P 1 (Note: The 601 PowerPC does not have a timebase frequency) 90 241.33 P 1 (, therefore on a 601 PowerPC the value) 341.36 241.33 P 1 (reported in this property shall be 1 billion \0501 x 10) 90 231.33 P 1 8 Q 0.8 (9) 297.21 235.33 P 1 10 Q 1 (\051 which represents the logical rate of the real time clock.) 301.21 231.33 P 4 F ("64-bit") 72 213.33 T 3 F 1 (pr) 90 198.33 P 1 (op-encoded-array) 98.52 198.33 P 1 F 1 (: ) 170.72 198.33 P 1 (This property) 90 180.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node is a 64-bit) 144.51 180.33 P 1 (implementation of the PowerPC architecture. The absence of this property indicates that the microprocessor) 90 170.33 P 1 (de\336ned by this CPU node is a 32 bit implementation of the PowerPC architecture) 90 160.33 P 4 F ("603-translation") 72 142.33 T 3 F 1 (pr) 90 127.33 P 1 (op-encoded-array) 98.52 127.33 P 1 F 1 (: ) 170.72 127.33 P 1 (This property) 90 109.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node uses the) 144.51 109.33 P 1 (PowerPC 603 de\336ned mechanism to update its T) 90 99.33 P 1 (ranslation Lookaside Buf) 291.92 99.33 P 1 (fers \050TLBs\051. The absence of this) 394.84 99.33 P 1 (property indicates that the PowerPC microprocessor de\336ned by this CPU node does not use the PowerPC) 90 89.33 P 1 (603 de\336ned mechanism to update its TLBs.) 90 79.33 P 52 692 54 720 R V FMENDPAGE %%EndPage: "14" 14 %%Page: "15" 15 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (15) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 4 10 Q 0 X 0 0 0 1 0 0 0 K ("603-power-management") 72 713.33 T 3 F 1 (pr) 90 698.33 P 1 (op-encoded-array) 98.52 698.33 P 1 F 1 (: ) 170.72 698.33 P 1 (This property) 90 680.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 680.33 P 1 (the PowerPC 603 de\336ned power management states. The absence of this property indicates that the) 90 670.33 P 1 (PowerPC microprocessor de\336ned by this CPU node does not support the PowerPC 603 de\336ned power) 90 660.33 P 1 (management states.) 90 650.33 P 4 F ("bus-frequency") 72 632.33 T 1 F 1 (Standard property) 90 617.33 P 1 (, encoded as with) 162.28 617.33 P 4 F 2.4 (encode-int) 238.21 617.33 P 1 F 1 (, that represents the speed \050in hertz\051 of this processor) 298.21 617.33 P 1 (\325) 518.64 617.33 P 1 (s) 521.42 617.33 P (bus.) 90 607.33 T 4 F ("32-64-bridge") 72 589.33 T 3 F 1 (pr) 90 574.33 P 1 (op-encoded-array) 98.52 574.33 P 1 F 1 (: ) 170.72 574.33 P 1 (This property) 90 556.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 556.33 P 1 (the "Bridge Facilities and Instructions for 64-bit Implementations" as described in an appendix of Book III) 90 546.33 P 1 (of [2]. The absence of this property indicates that the PowerPC microprocessor de\336ned by this CPU node) 90 536.33 P 1 (does not support these facilities and instructions.) 90 526.33 P 4 F ("emulation-assist-unit") 72 508.33 T 3 F 1 (pr) 90 493.33 P 1 (op-encoded-array) 98.52 493.33 P 1 F 1 (: ) 170.72 493.33 P 1 (This property) 90 475.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 475.33 P 1 (the emulation assist unit \050EAU\051. The absence of this property indicates that the PowerPC microprocessor) 90 465.33 P 1 (de\336ned by this CPU node does not implement the EAU.) 90 455.33 P 4 F ("external-control") 72 437.33 T 3 F 1 (pr) 90 422.33 P 1 (op-encoded-array) 98.52 422.33 P 1 F 1 (: ) 170.72 422.33 P 1 (This property) 90 404.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 404.33 P 1 (the External Control Facility as described in the "Optional Facilitites and Instructions" appendix of Book II) 90 394.33 P 1 (of [2]. The absence of his property indicates that the PowerPC microprocessor de\336ned by this CPU node) 90 384.33 P 1 (does not support the External Control Facility) 90 374.33 P 1 (.) 278.68 374.33 P 4 F ("general-purpose") 72 356.33 T 3 F 1 (pr) 90 341.33 P 1 (op-encoded-array) 98.52 341.33 P 1 F 1 (: ) 170.72 341.33 P 1 (This property) 90 323.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 323.33 P 1 (the \337oating point instructions) 90 313.33 P 2 F 1 (fsqrt) 214.01 313.33 P 1 F 1 ( and) 234.56 313.33 P 2 F 1 (fsqrts) 256 313.33 P 1 F 1 (. The absence of this property indicates that the PowerPC) 280.44 313.33 P 1 (microprocessor de\336ned by this CPU node does not support the \337oating point instructions) 90 303.33 P 2 F 1 (fsqrt) 461.05 303.33 P 1 F 1 ( and) 481.6 303.33 P 2 F 1 (fsqrts) 503.04 303.33 P 1 F 1 (.) 527.48 303.33 P 4 F ("reservation-granule-size") 72 285.33 T 1 F 1 (Standard property) 90 270.33 P 1 (, encoded as with) 162.28 270.33 P 2 F 1 (encode-int) 238.21 270.33 P 1 F 1 (, that represents the reservation granule size \050i.e., the) 282.65 270.33 P 1 (minimum size of lock variables\051 supported by this processor) 90 260.33 P 1 (, in bytes.) 339.24 260.33 P 4 F ("graphics") 72 242.33 T 3 F 1 (pr) 90 227.33 P 1 (op-encoded-array) 98.52 227.33 P 1 F 1 (: ) 170.72 227.33 P 1 (This property) 90 209.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 209.33 P 1 (the \337oating point instructions) 90 199.33 P 2 F 1 (st\336wx, fr) 214.01 199.33 P 1 (es, frsqrte,) 252.6 199.33 P 1 F 1 (and) 302.36 199.33 P 2 F 1 ( fsel) 316.8 199.33 P 1 F 1 (. The absence of this property indicates that the) 334.74 199.33 P 1 (PowerPC microprocessor de\336ned by this CPU node does not support the \337oating point instructions) 90 189.33 P 2 F 1 (st\336wx,) 502.33 189.33 P 1 (fr) 90 179.33 P 1 (es, frsqrte,) 97.59 179.33 P 1 F 1 (and) 147.35 179.33 P 2 F 1 ( fsel) 161.79 179.33 P 1 F 1 (.) 179.73 179.33 P 4 F ("performance-monitor") 72 161.33 T 3 F 1 (pr) 90 146.33 P 1 (op-encoded-array) 98.52 146.33 P 1 F 1 (: ) 170.72 146.33 P 1 (This property) 90 128.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 128.33 P 1 (the performance monitor functionality) 90 118.33 P 1 (. The absence of this property indicates that the PowerPC) 245.38 118.33 P 1 (microprocessor de\336ned by this CPU node does not support this performance monitor functionality) 90 108.33 P 1 (.) 494.65 108.33 P 4 F ("tlbia") 72 90.33 T 3 F 1 (pr) 90 75.33 P 1 (op-encoded-array) 98.52 75.33 P 1 F 1 (: ) 170.72 75.33 P 52 629 54 657 R V FMENDPAGE %%EndPage: "15" 15 %%Page: "16" 16 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (16) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 1 10 Q 0 X 0 0 0 1 0 0 0 K 1 (This property) 90 713.33 P 1 (, if present, indicates that the PowerPC microprocessor de\336ned by this CPU node implements) 144.51 713.33 P 1 (the) 90 703.33 P 2 F 1 (tlbia) 105.72 703.33 P 1 F 1 ( insruction. The absence of this property indicates that the PowerPC microprocessor de\336ned by) 125.17 703.33 P 1 (this CPU node does not support the) 90 693.33 P 2 F 1 (tlbia) 241.17 693.33 P 1 F 1 ( insruction.) 260.62 693.33 P 2 12 Q (5.1.5. TLB pr) 72 670 T (operties) 143.8 670 T 1 10 Q 1.41 (Since the PowerPC architecture de\336nes the MMU as being part of the processor) 72 653.33 P 1.41 (, the properties de\336ned by Sec-) 408.51 653.33 P 1 (tion 3.6.5 of [1] and the following MMU-related properties shall be presented under "cpu" nodes.) 72 641.33 P 4 F ("tlb-size") 72 624.33 T 1 F 1 (Standard property) 90 609.33 P 1 (, encoded as with) 162.28 609.33 P 4 F 2.4 (encode-int) 238.21 609.33 P 1 F 1 (, that represents the total number of TLB entries.) 298.21 609.33 P 4 F ("tlb-sets") 72 591.33 T 1 F 1 (Standard property) 90 576.33 P 1 (, encoded as with encode-int, that represents the number of associativity sets of the TLB.) 162.28 576.33 P 1 (A value of 1 indicates that the TLB is fully-associative.) 90 566.33 P 4 F ("tlb-split") 72 548.33 T 1 F 1 (This property) 90 533.33 P 1 (, if present, shall indicate that the TLB has a split or) 144.51 533.33 P 1 (ganization. The absence of this property) 362.81 533.33 P 1 (shall indicate that the TLB has a uni\336ed or) 90 523.33 P 1 (ganization.) 268.36 523.33 P 4 F ("d-tlb-size") 72 505.33 T 1 F 1 (Standard property) 90 490.33 P 1 (, encoded as with encode-int, that represents the total number of d-TLB entries.) 162.28 490.33 P 4 F ("d-tlb-sets") 72 472.33 T 1 F 0.79 (Standard property) 90 457.33 P 0.79 (, encoded as with encode-int, that represents the number of associativity sets of the d-TLB.) 162.07 457.33 P 1 (A value of 1 indicates that the d-TLB is fully-associative.) 90 447.33 P 4 F ("i-tlb-size") 72 429.33 T 1 F 1 (Standard property) 90 414.33 P 1 (, encoded as with encode-int, that represents the total number of i-TLB entries.) 162.28 414.33 P 4 F ("i-tlb-sets") 72 396.33 T 1 F 0.93 (Standard property) 90 381.33 P 0.93 (, encoded as with encode-int, that represents the number of associativity sets of the i-TLB.) 162.21 381.33 P 1 (A value of 1 indicates that the i-TLB is fully-associative.) 90 371.33 P 2 12 Q (5.1.6. Internal \050L1\051 cache pr) 72 348 T (operties) 218.44 348 T 1 10 Q 1 (The PowerPC architecture de\336nes a Harvard-style cache architecture; however) 72 331.33 P 1 (, uni\336ed caches are an) 395.05 331.33 P 1 (implementation option. All of the PowerPC cache instructions act upon a cache "block" \050also referred to as a) 72 319.33 P 1 (cache "line"\051. The internal \050also referred to as "L1"\051 caches of PowerPC processors are represented in the Open) 72 307.33 P 1 (Firmware device tree by the following properties contained under) 72 295.33 P 5 F 2.4 ("cpu") 346.22 295.33 P 1 F 1 ( nodes.) 376.22 295.33 P 4 F ("cache-unif) 72 276.33 T (ied") 138 276.33 T 1 F 1 (This property) 90 261.33 P 1 (, if present, indicates that the internal cache has a uni\336ed or) 144.51 261.33 P 1 (ganization. Absence of this) 392.78 261.33 P 1 (property indicates that the internal caches are implemented as separate instruction and data caches.) 90 251.33 P 4 F ("i-cache-size") 72 233.33 T 1 F 1 (Standard property) 90 218.33 P 1 (, encoded as with) 162.28 218.33 P 4 F 2.4 (encode-int) 238.21 218.33 P 1 F 1 (, that represents the total size \050in bytes\051 of the internal) 298.21 218.33 P 1 (instruction cache.) 90 208.33 P 4 F ("i-cache-sets") 72 190.33 T 1 F 1 (Standard property) 90 175.33 P 1 (, encoded as with) 162.28 175.33 P 4 F 2.4 (encode-int) 238.21 175.33 P 1 F 1 (, that represents number of associativity sets of the) 298.21 175.33 P 1 (internal instruction cache. A value of 1 signi\336es that the instruction cache is fully associative.) 90 165.33 P 4 F ("i-cache-block-size") 72 147.33 T 1 F 0.86 (Standard property) 90 132.33 P 0.86 (, encoded as with) 162.14 132.33 P 4 F 2.05 (encode-int) 237.49 132.33 P 1 F 0.86 (, that represents the internal instruction cache's block size,) 297.49 132.33 P 1 (in bytes.) 90 122.33 P 4 F ("d-cache-size") 72 104.33 T 1 F 1 (Standard property) 90 89.33 P 1 (, encoded as with) 162.28 89.33 P 4 F 2.4 (encode-int) 238.21 89.33 P 1 F 1 (, that represents the total size \050in bytes\051 of the internal) 298.21 89.33 P 1 (data cache.) 90 79.33 P 52 368 54 555 R V FMENDPAGE %%EndPage: "16" 16 %%Page: "17" 17 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (17) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 4 10 Q 0 X 0 0 0 1 0 0 0 K ("d-cache-sets") 72 713.33 T 1 F 1 (Standard property) 90 698.33 P 1 (, encoded as with) 162.28 698.33 P 4 F 2.4 (encode-int) 238.21 698.33 P 1 F 1 (, that represents number of associativity sets of the) 298.21 698.33 P 1 (internal data cache. A value of 1 signi\336es that the data cache is fully associative.) 90 688.33 P 4 F ("d-cache-block-size") 72 670.33 T 1 F 1 (Standard property) 90 655.33 P 1 (, encoded as with) 162.28 655.33 P 4 F 2.4 (encode-int) 238.21 655.33 P 1 F 1 (, that represents the internal \050L1\051 data cache's block size,) 298.21 655.33 P 1 (in bytes.) 90 645.33 P 4 F ("l2-cache") 72 627.33 T 1 F 1 (Standard property) 90 612.33 P 1 (, encoded as with) 162.28 612.33 P 4 F 2.4 (encode-int) 238.21 612.33 P 1 F 1 (, that represents the next level of cache in the memory) 298.21 612.33 P (hierarchy) 90 602.33 T (.) 127.11 602.33 T 1 (Absence of this property indicates that no further levels of cache are present. If present, its value is the) 90 584.33 P 3 F 1 (phandle) 90 574.33 P 1 F 1 ( of the device node that represents the next level of cache.) 122.22 574.33 P 4 F ("i-cache-line-size") 72 556.33 T 1 F 1 (Standard property) 90 541.33 P 1 (, encoded as with encode-int, that represents the internal instruction cache's line size, in) 162.28 541.33 P 1 (bytes, if dif) 90 531.33 P 1 (ferent than its block size.) 137.65 531.33 P 4 F ("d-cache-line-size") 72 513.33 T 1 F 1 (Standard property) 90 498.33 P 1 (, encoded as with encode-int, that represents the internal data cache's line size, in bytes, if) 162.28 498.33 P 1 (dif) 90 488.33 P 1 (ferent than its block size.) 100.93 488.33 P 2 9 Q 0.9 (Note: If this is a uni\336ed cache, the corr) 108 471 P 0.9 (esponding i- and d- sizes must be equal.) 263.77 471 P 2 12 Q (5.1.7. Memory Management Unit pr) 72 447 T (operties) 259.75 447 T 1 10 Q 1.51 (T) 72 430.33 P 1.51 (o aid a client in "taking over" the translation mechanism and still interact with Open Firmware \050via the clie) 77.41 430.33 P 3 F 1.51 (nt) 532.22 430.33 P 1.78 (interface) 72 418.33 P 1 F 1.78 (\051, the client needs to know what translations have been established by Open Firmware. The following) 107.55 418.33 P 1 (standard property shall exist within the package to which the "mmu" property of the /chosen package refers.) 72 406.33 P 4 F ("translations") 72 389.33 T 1 F 1 (This property) 90 374.33 P 1 (, consisting of sets of translations, de\336nes the currently active translations that have been) 144.51 374.33 P 1 (established by Open Firmware \050e.g., using map\051. Each set has the following format:) 90 364.33 P 5 F 2.4 (\050virt size phys mode \051) 126 346.33 P 1 F 1 (Each value is encoded as with) 90 328.33 P 4 F 2.4 (encode-int) 218.75 328.33 P 1 F 1 (.) 278.75 328.33 P 2 14 Q (5.2. Ancillary \050L2,L3...\051 cache node pr) 72 299.67 T (operties) 301.96 299.67 T 1 10 Q 1 (Some systems might include secondary \050L2\051 or tertiary \050L3\051, etc. cache\050s\051. As with the L1 caches, they can be) 72 282.33 P 1 (implemented as either Harvard-style or uni\336ed. Unlike the L1 properties, that are contained within the) 72 270.33 P 5 F 2.4 ("cpu") 498.32 270.33 P 1 F 1 (nodes, the properties of ancillary caches are contained within other device tree nodes.) 72 258.33 P 1 (The following properties de\336ne the characteristics of such ancillary caches. These properties) 72 239.33 P 3 F 1 (shall) 456.96 239.33 P 1 F 1 ( be contained) 476.41 239.33 P 1 (as a child node of one of the CPU nodes; this is to allow path-name access to the node. All) 72 227.33 P 5 F 2.4 ("cpu") 456.68 227.33 P 1 F 1 ( nodes that) 486.68 227.33 P 1 (share the same ancillary cache \050including the cpu node under which the ancillary cache node is contained\051) 72 215.33 P 3 F 1 (shall) 515.83 215.33 P 1 F 1 (contain an) 72 203.33 P 5 F 2.4 ("l2-cache") 117.88 203.33 P 1 F 1 ( property whose value is the) 177.88 203.33 P 6 F 2.4 (phandle) 298.86 203.33 P 1 F 1 ( of that ancillary cache node.) 340.86 203.33 P 2 9 Q 0.9 (Note: The) 108 185 P 5 F 2.16 ("l2-cache") 150.29 185 P 2 F 0.9 ( pr) 204.29 185 P 0.9 (operty shall be used in one level of the cache hierar) 216.28 185 P 0.9 (chy to r) 420.61 185 P 0.9 (ep-) 451.74 185 P 0.9 (r) 108 175 P 0.9 (esent the next level. The device node for a subsequent level shall appear as a child of one) 111.83 175 P 0.9 (of the caches in the hierar) 108 165 P 0.9 (chy to allow path-name traversal.) 211.57 165 P 4 10 Q ("device_type") 72 150.33 T 1 F 1 (Open Firmware Standard property; the device_type of ancillary cache nodes) 90 135.33 P 3 F 1 (shall) 407.7 135.33 P 1 F 1 ( be) 427.15 135.33 P 5 F 2.4 ("cache") 443.59 135.33 P 1 F 1 (.) 485.59 135.33 P 4 F ("cache-unif) 72 117.33 T (ied") 138 117.33 T 1 F 1 (This property) 90 102.33 P 1 (, if present, indicates that the cache at this node has a uni\336ed or) 144.51 102.33 P 1 (ganization. Absence of this) 410.34 102.33 P 1 (property indicates that the caches at this node are implemented as separate instruction and data caches.) 90 92.33 P 52 468 54 563 R V 52 343 54 353 R V 52 132 54 157 R V FMENDPAGE %%EndPage: "17" 17 %%Page: "18" 18 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (18) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 4 10 Q 0 X 0 0 0 1 0 0 0 K ("i-cache-size") 72 713.33 T 1 F 1 (Standard property) 90 698.33 P 1 (, encoded as with) 162.28 698.33 P 4 F 2.4 (encode-int) 238.21 698.33 P 1 F 1 (, that represents the total size \050in bytes\051 of the instruction) 298.21 698.33 P 1 (cache at this node.) 90 688.33 P 4 F ("i-cache-sets") 72 670.33 T 1 F 1 (Standard property) 90 655.33 P 1 (, encoded as with) 162.28 655.33 P 4 F 2.4 (encode-int) 238.21 655.33 P 1 F 1 (, that represents number of associativity sets of the) 298.21 655.33 P 1 (instruction cache at this node. A value of 1 signi\336es that the instruction cache is fully associative.) 90 645.33 P 4 F ("d-cache-size") 72 627.33 T 1 F 1 (Standard property) 90 612.33 P 1 (, encoded as with) 162.28 612.33 P 4 F 2.4 (encode-int) 238.21 612.33 P 1 F 1 (, that represents the total size \050in bytes\051 of the data cache) 298.21 612.33 P 1 (at this node.) 90 602.33 P 4 F ("d-cache-sets") 72 584.33 T 1 F 1 (Standard property) 90 569.33 P 1 (, encoded as with) 162.28 569.33 P 4 F 2.4 (encode-int) 238.21 569.33 P 1 F 1 (, that represents number of associativity sets of the) 298.21 569.33 P 1 (instruction cache at this node. A value of 1 signi\336es that the instruction cache is fully associative.) 90 559.33 P 4 F ("l2-cache") 72 541.33 T 1 F 1 (Standard property) 90 526.33 P 1 (, encoded as with) 162.28 526.33 P 4 F 2.4 (encode-int) 238.21 526.33 P 1 F 1 (, that represents the next level of cache in the memory) 298.21 526.33 P (hierarchy) 90 516.33 T (.) 127.11 516.33 T 1 (Absence of this property indicates that no further levels of cache are present. If present, its value is the) 90 498.33 P 3 F 1 (phandle) 90 488.33 P 1 F 1 ( of the device node that represents the cache at the next level.) 122.22 488.33 P 2 14 Q (6. Methods) 72 459.67 T 1 10 Q 1 (This section describes the additional standard methods required of a PowerPC Open Firmware implementation.) 72 442.33 P 2 14 Q (6.1. MMU r) 72 411.67 T (elated methods) 146 411.67 T 1 10 Q 1 (The MMU methods de\336ned by section 3.6.5. of [1]) 72 394.33 P 3 F 1 (shall) 288.2 394.33 P 1 F 1 ( be implemented by CPU nodes. The value of the) 307.65 394.33 P 6 F 2.4 (mode) 72 382.33 P 1 F 1 ( parameter for the relevant methods \050e.g.,) 96 382.33 P 4 F 2.4 (map) 270.73 382.33 P 1 F 1 (\051) 288.73 382.33 P 3 F 1 (shall) 295.56 382.33 P 1 F 1 ( be the value that is contained within PTEs that) 315.01 382.33 P 1 (control W) 72 370.33 P 1 (rite-through, Cache-Inhibit, Memory-coherent, Guarded and the 2 protection bits; thus, its format is:) 112.87 370.33 P 4 F 2.4 (WIMGxPP) 72 358.33 P 1 F 1 (, where x is a reserved bit that) 112.89 358.33 P 3 F 1 (shall) 243.36 358.33 P 1 F 1 ( be 0. In order for I/O accesses to be properly performed in a) 262.81 358.33 P 1 (PowerPC system, address ranges that are mapped by) 72 346.33 P 4 F 2.4 (map-in) 293.02 346.33 P 3 F 1 (shall) 332.52 346.33 P 1 F 1 ( be marked as Cache-Inhibited, Guarded.) 351.97 346.33 P 1 (The default mode \050i.e., the mode speci\336ed when the value of the) 72 327.33 P 3 F 1 (mode) 343.67 327.33 P 1 F 1 ( ar) 365.33 327.33 P 1 (gument is -1\051 for the) 376.42 327.33 P 4 F 2.4 (map-in) 466.13 327.33 P 1 F 1 ( and) 502.13 327.33 P 4 F 2.4 (modify) 72 315.33 P 1 F 1 ( MMU methods of CPU nodes is de\336ned as follows:) 108 315.33 P 1 (If the beginning of the physical address range af) 72 296.33 P 1 (fected by the operation refers to system memory) 272.55 296.33 P 1 (, the values for) 472.47 296.33 P 4 F 2.4 (WIMGxPP) 72 284.33 P 3 F 1 (shall) 117.5 284.33 P 1 F 1 ( be W=0, I=0, M=0, G=1, PP=10.) 136.95 284.33 P 1 (If the beginning of the physical address range af) 72 265.33 P 1 (fected by the operation refers to an I/O address, the values for) 272.55 265.33 P 1 (WIMGxPP) 72 253.33 P 3 F 1 (shal) 120.5 253.33 P 1 F 1 (l be W=1, I=1, M=0, G=1, PP=10.) 137.17 253.33 P 2 14 Q (7. Client Interface Requir) 72 222.67 T (ements) 229.22 222.67 T 1 10 Q 1 (A PowerPC Open Firmware implementation) 72 205.33 P 3 F 1 (shall) 257.82 205.33 P 1 F 1 ( implement a client interface \050as de\336ned in chapter 6 of [1]\051) 277.27 205.33 P 1 (according to the speci\336cations contained within this section.) 72 193.33 P 2 14 Q (7.1. Calling Conventions) 72 162.67 T 1 10 Q 0.98 (T) 72 145.33 P 0.98 (o invoke a client interface service, a) 77.41 145.33 P 3 F 0.98 (client pr) 230.87 145.33 P 0.98 (ogram) 265.09 145.33 P 1 F 0.98 (constructs a client interface) 294.67 145.33 P 3 F 0.98 (ar) 410.77 145.33 P 0.98 (gument array) 419.29 145.33 P 1 F 0.98 ( as speci\336ed in) 474.43 145.33 P 1 (the core Open Firmware document, places its address in) 72 133.33 P 4 F 2.4 (r3) 307.62 133.33 P 1 F 1 ( and transfers to the) 319.62 133.33 P 3 F 1 (client interface handler) 405.99 133.33 P 1 F 1 (, with) 501.47 133.33 P 1 (the return address in) 72 121.33 P 4 F 2.4 (lr) 159.87 121.33 P 1 F 1 (. \050A typical way of accomplishing this is to copy the) 171.32 121.33 P 3 F 1 (client interface handler) 393.97 121.33 P 1 F 1 ('s address) 489.85 121.33 P 1 (into) 72 109.33 P 4 F 2.4 (ctr) 91.06 109.33 P 1 F 1 (and executing a) 117.46 109.33 P 4 F 2.4 (bctrl) 185.72 109.33 P 1 F 1 (.\051) 215.72 109.33 P 1 (The term "preserved" below shall mean that the register has the same value when returning as it did when the) 72 90.33 P 1 (call was made.) 72 78.33 P 52 312 54 353 R V 52 75 54 172 R V FMENDPAGE %%EndPage: "18" 18 %%Page: "19" 19 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (19) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 2 10 Q 0 X 0 0 0 1 0 0 0 K (Notes) 72 418.83 T 1 (1.) 108 403.83 P 1 F 1 (Only the non-volatile \336elds \050) 119 403.83 P 5 F 2.4 (cr2-cr4) 238.55 403.83 P 1 F 1 (\051 need to be preserved.) 280.55 403.83 P 2 F 1 (2.) 108 387.83 P 1 F 1 (As de\336ned by section 6.3.1. of [1].) 119 387.83 P 2 F 1 (3.) 108 371.83 P 1 F 1 ( Other special purpose registers) 115.5 371.83 P 0.86 (The) 72 355.83 P 3 F 0.86 (client interface handler) 90.91 355.83 P 0.86 (shall) 189.87 355.83 P 1 F 0.86 ( perform the service speci\336ed by the contents of the ar) 209.32 355.83 P 0.86 (gument array that begins) 434.91 355.83 P 1 (at the address in) 72 343.83 P 4 F 2.4 (r3) 143.21 343.83 P 1 F 1 (, place the return value \050indicating success or failure of the attempt to invoke the client) 155.21 343.83 P 1 (interface service\051 back into) 72 331.83 P 4 F 2.4 (r3) 187.07 331.83 P 1 F 1 (, and return to the) 199.07 331.83 P 3 F 1 (client pr) 277.39 331.83 P 1 (ogram) 311.63 331.83 P 1 F 1 (. This is typically done by a Branch to Link) 337.74 331.83 P 1 (Register \050) 72 319.83 P 4 F 2.4 (blr) 112.16 319.83 P 1 F 1 (\051.) 130.16 319.83 P 1 (The) 72 300.83 P 3 F 1 (client interface handler) 91.05 300.83 P 1 (shall) 190.43 300.83 P 1 F 1 ( preserve the contents of the Stack Pointer \050) 209.88 300.83 P 4 F 2.4 (r) 392.29 300.83 P 2 F 1 (1) 398.29 300.83 P 1 F 1 (\051, T) 403.29 300.83 P 1 (OC Pointer \050) 418.55 300.83 P 4 F 2.4 (r2) 471.66 300.83 P 1 F 1 (\051, Condition) 483.66 300.83 P 1 (Register \050) 72 288.83 P 4 F 2.4 (cr) 112.16 288.83 P 1 F 1 (\051 all non-volatile registers \050) 124.16 288.83 P 4 F 2.4 (r13) 237.03 288.83 P 5 F 2.4 (-) 255.03 288.83 P 4 F 2.4 (r31) 261.03 288.83 P 1 F 1 (\051 and all special purpose registers except) 279.03 288.83 P 4 F 2.4 (lr) 450.71 288.83 P 1 F 1 (,) 462.31 288.83 P 4 F 2.4 (ctr) 468.31 288.83 P 1 F 1 (and) 489.81 288.83 P 4 F 2.4 (xer) 507.75 288.83 P 1 F 1 (.) 525.2 288.83 P 1 (The preservation of) 72 269.83 P 4 F 2.4 (r2) 155.81 269.83 P 1 F 1 ( allows T) 167.81 269.83 P 1 (OC-based client programs to function correctly) 206.85 269.83 P 1 (. Open Firmware) 400.33 269.83 P 3 F 1 (shall not) 473.87 269.83 P 1 F 1 (depend upon whether its client is T) 72 257.83 P 1 (OC-based or not. If the client interface handler) 218.36 257.83 P 1 (, itself, is T) 412.13 257.83 P 1 (OC-based, it must) 460.23 257.83 P 1 (provide for the appropriate initialization of its) 72 245.83 P 4 F 2.4 (r2) 264.81 245.83 P 1 F 1 (.) 276.81 245.83 P 2 14 Q (8. Client Pr) 72 215.17 T (ogram Requir) 144.07 215.17 T (ements) 228.2 215.17 T (8.1. Load Addr) 72 183.17 T (ess) 166.26 183.17 T 1 10 Q 1 (The client\325) 72 165.83 P 1 (s load address is speci\336ed by the value of the) 116.05 165.83 P 4 F 2.4 (load-base) 308.8 165.83 P 1 F 1 ( Con\336guration V) 362.8 165.83 P 1 (ariable. The value of) 431.47 165.83 P 2 F 1 (load-base) 72 153.83 P 1 F 1 ( de\336nes the default load address for) 112.56 153.83 P 3 F 1 (client pr) 264.25 153.83 P 1 (ogram) 298.49 153.83 P 1 F 1 (s when using the) 324.6 153.83 P 4 F 2.4 (load) 398.04 153.83 P 1 F 1 ( method.) 422.04 153.83 P 2 F 1 (Load-base) 465.04 153.83 P 1 F 1 (shall) 512.99 153.83 P 1 (be a real address in real mode or a virtual address in virtual mode. Note that this address represents the area) 72 141.83 P 1 (into which the client program \336le will be read by) 72 129.83 P 2 F 1 (load) 280.31 129.83 P 1 F 1 (; it does not correspond to the addresses at which the) 298.65 129.83 P 0.9 (program will be executed. All of physical memory from) 72 117.83 P 2 F 0.9 (load-base) 306.69 117.83 P 1 F 0.9 ( to either the start of Open Firmware physical) 347.25 117.83 P 1 (memory or the end of physical memory) 72 105.83 P 1 (, whichever comes \336rst, shall be available for loading the client program.) 235.66 105.83 P 109 701.5 179.5 719 R 6 X V 2 12 Q 0 X (Register\050s\051) 114 705 T 180.5 701.5 323.5 719 R 6 X V 0 X ( V) 186 705 T (alue -- r) 211.56 705 T (eal-mode) 252 705 T 324.5 701.5 467.5 719 R 6 X V 0 X (V) 330 705 T (alue -- virt-mode) 337.56 705 T 468.5 701.5 512 719 R 6 X V 0 X (Notes) 474 705 T 4 10 Q (msr) 114 689.33 T 2 F (client interface shall pr) 186 689.33 T (eserve) 284.42 689.33 T -0.25 (client interface shall not modify) 330 689.33 P 4 F (cr) 114 674.33 T 2 F (client interface shall pr) 186 674.33 T (eserve) 284.42 674.33 T (same as r) 330 674.33 T (eal-mode) 369.81 674.33 T (1) 481.5 674.33 T 4 F (r1-r2) 114 659.33 T 2 F (client interface shall pr) 186 659.33 T (eserve) 284.42 659.33 T (same as r) 330 659.33 T (eal-mode) 369.81 659.33 T 4 F (r3) 114 644.33 T 2 F (argument array addr) 186 644.33 T (ess on cli-) 276.92 644.33 T (ent interface entry) 186 632.33 T (same as r) 330 644.33 T (eal-mode) 369.81 644.33 T (2) 481.5 644.33 T (r) 186 617.33 T (esult value \050) 190.26 617.33 T 4 F (true) 241.37 617.33 T 2 F ( or) 265.37 617.33 T 4 F (false) 279.81 617.33 T 2 F (\051) 309.81 617.33 T (on client interface r) 186 605.33 T (eturn) 269.41 605.33 T (same as r) 330 617.33 T (eal-mode) 369.81 617.33 T (2) 481.5 617.33 T 4 F (r13-r31) 114 590.33 T 2 F (client interface shall pr) 186 590.33 T (eserve) 284.42 590.33 T (same as r) 330 590.33 T (eal-mode) 369.81 590.33 T 4 F (sprg0-) 114 573.33 T (sprg3) 114 561.33 T 2 F (client interface shall pr) 186 573.33 T (eserve) 284.42 573.33 T -0.25 (client interface shall not modify) 330 573.33 P 4 F (fpscr) 114 546.33 T 2 F (client interface shall pr) 186 546.33 T (eserve) 284.42 546.33 T (same as r) 330 546.33 T (eal-mode) 369.81 546.33 T 4 F (f0-f31) 114 529.33 T 2 F (client interface shall pr) 186 529.33 T (eserve) 284.42 529.33 T (same as r) 330 529.33 T (eal-mode) 369.81 529.33 T 4 F (lr) 114 512.33 T 1 F (,) 125.6 512.33 T 4 F (ctr) 114 500.33 T 1 F (,) 131.6 500.33 T 4 F (xer) 114 488.33 T 2 F (unde\336ned) 186 512.33 T (same as r) 330 512.33 T (eal-mode) 369.81 512.33 T (sr0-sr15) 114 473.33 T (client interface shall pr) 186 473.33 T (eserve) 284.42 473.33 T -0.25 (client interface shall not modify) 330 473.33 P (Other SPRs) 114 458.33 T (client interface shall pr) 186 458.33 T (eserve) 284.42 458.33 T (same as r) 330 458.33 T (eal-mode) 369.81 458.33 T 1 F (3) 474 458.33 T 1 7.5 Q (T) 252.75 441 T (able 1.) 256.81 441 T ( Register usage conventions) 284.3 441 T 108 719 108 455 2 L V 2 H 0 Z N 180 721 180 453 2 L V 1 H N 324 721 324 453 2 L V N 468 721 468 453 2 L V N 513 719 513 455 2 L V 2 H N 107 720 514 720 2 L V N 109 701.25 512 701.25 2 L V 0.5 H N 109 698.75 512 698.75 2 L V N 107 685 514 685 2 L V 1 H N 107 670 514 670 2 L V N 107 655 514 655 2 L V N 179.5 628 514 628 2 L 4 X V N 107 601 514 601 2 L 0 X V N 107 584 514 584 2 L V N 107 557 514 557 2 L V N 107 540 514 540 2 L V N 107 523 514 523 2 L V N 107 484 514 484 2 L V N 107 469 514 469 2 L V N 107 454 514 454 2 L V 2 H N 52 368.5 54 425.5 R V 52 328.5 54 350.5 R V 52 266.5 54 307.5 R V 52 242.5 54 252.5 R V 52 138.5 54 160.5 R V 52 102.5 54 124.5 R V 52 701 54 713 R V 52 701 54 713 R V 52 686 54 696 R V 52 686 54 696 R V 52 686 54 696 R V 52 671 54 681 R V 52 671 54 681 R V 52 671 54 681 R V 52 656 54 666 R V 52 656 54 666 R V 52 656 54 666 R V 52 641 54 651 R V 52 641 54 651 R V 52 614 54 624 R V 52 587 54 597 R V 52 587 54 597 R V 52 587 54 597 R V 52 558 54 580 R V 52 570 54 580 R V 52 570 54 580 R V 52 543 54 553 R V 52 543 54 553 R V 52 543 54 553 R V 52 526 54 536 R V 52 526 54 536 R V 52 526 54 536 R V 52 485 54 519 R V 52 509 54 519 R V 52 470 54 480 R V 52 470 54 480 R V 52 470 54 480 R V 52 455 54 465 R V 52 455 54 465 R V FMENDPAGE %%EndPage: "19" 19 %%Page: "20" 20 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (20) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 2 14 Q 0 X 0 0 0 1 0 0 0 K (8.2. Initial Pr) 72 710.67 T (ogram State) 154.59 710.67 T 1 10 Q 1 (This section de\336nes the "initial program state", the execution environment that exists when the \336rst machine) 72 693.33 P 1 (instruction of a) 72 681.33 P 3 F 1 (client pr) 138.05 681.33 P 1 (ogram) 172.29 681.33 P 1 F 1 ( of the format speci\336ed above begins execution. Many aspects of the "initial) 198.4 681.33 P 1 (program state" are established by) 72 669.33 P 4 F 2.4 (init-program) 212.44 669.33 P 1 F 1 (, which sets the) 284.44 669.33 P 3 F 1 (saved pr) 352.6 669.33 P 1 (ogram state) 387.39 669.33 P 1 F 1 ( so that subsequent) 435.89 669.33 P 1 (execution of) 72 657.33 P 2 F 1 (go) 126.21 657.33 P 1 F 1 ( will begin execution of the) 136.21 657.33 P 3 F 1 (client pr) 254.42 657.33 P 1 (ogram) 288.66 657.33 P 1 F 1 ( with the speci\336ed environment.) 314.77 657.33 P 2 12 Q (8.2.1. Initial Register V) 72 632 T (alues) 192.55 632 T 1 10 Q 1 (Upon entry to the client program, the following registers shall contain the following values:) 72 615.33 P 2 F (Notes:) 72 297.83 T 0.85 (1) 108 282.83 P 1 F 0.85 (. Open Firmware will typically require the use of external interrupts for its) 113 282.83 P 3 F 0.85 (user interface) 424.03 282.83 P 1 F 0.85 (.) 480.15 282.83 P 1 (However) 108 272.83 P 1 (, when a) 144.25 272.83 P 3 F 1 (client pr) 183.35 272.83 P 1 (ogram) 217.59 272.83 P 1 F 1 ( is invoked, external interrupts) 243.7 272.83 P 3 F 1 (shall) 373.13 272.83 P 1 F 1 ( be disabled. If a) 392.58 272.83 P 3 F 1 (cli-) 466.45 272.83 P 1 (ent pr) 108 262.83 P 1 (ogram) 132.24 262.83 P 1 F 1 ( causes the invocation of the user interface, external interrupts) 158.35 262.83 P 3 F 1 (may) 419.12 262.83 P 1 F 1 ( be re-) 435.78 262.83 P (enabled.) 108 252.83 T 2 F 1 (2) 108 236.83 P 1 F 1 (. The 601 processor uses a dif) 113 236.83 P 1 (ferent mechanism for controlling the endian-mode of the) 237.96 236.83 P 1 (processor) 108 226.83 P 1 (. On the 601, the LE bit is contained in the HID0 register; this bit controls the) 145.77 226.83 P 1 (endian-mode of both program and privileged states.) 108 216.83 P 2 F 1 (3) 108 200.83 P 1 F 1 (. Open Firmware does not make any assumptions about whether a client program is) 113 200.83 P 1 (T) 108 190.83 P 1 (OC-based or not. It is the responsibility of the client program to set) 113.93 190.83 P 4 F 2.4 (r2) 398.02 190.83 P 1 F 1 ( to its T) 410.02 190.83 P 1 (OC, if) 443.68 190.83 P (necessary) 108 180.83 T (.) 146.22 180.83 T 2 F 1 (4) 108 164.83 P 1 F 1 (. As de\336ned in the relevant section of the platform binding.) 113 164.83 P 2 12 Q (8.2.2. Initial Stack) 72 141.5 T 1 10 Q 1 (Client programs) 72 124.83 P 3 F 1 (shall) 141.22 124.83 P 1 F 1 ( be invoked with a valid stack pointer \050) 160.67 124.83 P 4 F 2.4 (r1) 324.76 124.83 P 1 F 1 (\051 with at least 32K bytes of memory available) 336.76 124.83 P 1 (for stack growth. The stack pointer) 72 113.83 P 3 F 1 (shall) 220.47 113.83 P 1 F 1 ( be 16-byte aligned, reserving suf) 239.92 113.83 P 1 (\336cient room for a linkage area \05032) 378.6 113.83 P 1 (bytes above the address in) 72 102.83 P 4 F 2.4 (r1) 184.48 102.83 P 1 F 1 (\051. If the system is executing in Real-Mode, the value in) 196.48 102.83 P 4 F 2.4 (r1) 429.95 102.83 P 1 F 1 ( is a real address; if in) 441.95 102.83 P 1 (V) 72 91.83 P 1 (irtual-Mode, the address in) 78.62 91.83 P 4 F 2.4 (r1) 192.88 91.83 P 1 F 1 ( is a mapped virtual address.) 204.88 91.83 P 151.66 587.5 208.84 601 R 6 X V 2 F 0 X (Register\050s\051) 156.66 590.33 T 209.84 587.5 460.84 601 R 6 X V 0 X ( V) 215.34 590.33 T (alue) 244.14 590.33 T 461.84 587.5 496.34 601 R 6 X V 0 X (Notes) 467.34 590.33 T (msr) 156.66 577.33 T (EE=0, interrupts disabled) 215.34 577.33 T ( 1) 467.34 577.33 T (PR=0, supervisor state) 215.34 564.33 T (FP=1, \337oating point enabled) 215.34 549.33 T (ME=1, machine checks enabled) 215.34 534.33 T (FE0,FE1=0, \337oating point exceptions disabled) 215.34 519.33 T (IP) 215.34 504.33 T (, see section) 224.42 504.33 T (8.4.) 276.63 504.33 T (IR,DR, see section) 215.34 489.33 T (4.2.1.) 295.6 489.33 T (SF=0, 32-bit mode) 215.34 474.33 T (ILE,LE, little endian support) 215.34 459.33 T ( 2) 467.34 459.33 T (r1) 156.66 446.33 T (see section) 215.34 446.33 T (8.2.2.) 262.55 446.33 T (r2) 156.66 431.33 T (0) 215.34 431.33 T ( 3) 467.34 431.33 T (r3) 156.66 418.33 T (r) 215.34 418.33 T (eserved for platform binding) 219.6 418.33 T ( 4) 467.34 418.33 T (r4) 156.66 405.33 T (r) 215.34 405.33 T (eserved for platform binding) 219.6 405.33 T (4) 470.34 404 T (r5) 156.66 390.33 T (see section) 215.34 390.33 T (8.2.3.) 262.55 390.33 T (r6,r7) 156.66 375.33 T (see section) 215.34 375.33 T (8.2.4.) 262.55 375.33 T (Other) 156.66 360.33 T (user mode) 156.66 348.33 T (r) 156.66 336.33 T (egisters) 160.92 336.33 T (0) 215.34 360.33 T 1 7.5 Q (T) 273.96 319 T (able 2.) 278.01 319 T ( Initial Register V) 305.51 319 T (alues) 358.63 319 T 150.66 601 150.66 333 2 L V 2 H 0 Z N 209.34 603 209.34 331 2 L V 1 H N 461.34 603 461.34 331 2 L V N 497.34 601 497.34 333 2 L V 2 H N 149.66 602 498.34 602 2 L V N 151.66 587.25 496.34 587.25 2 L V 0.5 H N 151.66 584.75 496.34 584.75 2 L V N 208.84 573 498.34 573 2 L 4 X V 1 H N 208.84 558 498.34 558 2 L V N 208.84 543 498.34 543 2 L V N 208.84 528 498.34 528 2 L V N 208.84 513 498.34 513 2 L V N 208.84 498 498.34 498 2 L V N 208.84 483 498.34 483 2 L V N 208.84 468 498.34 468 2 L V N 149.66 455 498.34 455 2 L 0 X V N 149.66 440 498.34 440 2 L V N 149.66 427 498.34 427 2 L V N 149.66 414 498.34 414 2 L V N 149.66 399 498.34 399 2 L V N 149.66 384 498.34 384 2 L V N 149.66 369 498.34 369 2 L V N 149.66 332 498.34 332 2 L V 2 H N 52 187.5 54 197.5 R V 52 121.5 54 131.5 R V 52 88.5 54 109.5 R V 52 574 54 584 R V 52 443 54 453 R V 52 428 54 438 R V 52 415 54 425 R V 52 402 54 412 R V 52 387 54 397 R V 52 372 54 382 R V 52 333 54 367 R V 52 357 54 367 R V FMENDPAGE %%EndPage: "20" 20 %%Page: "21" 21 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (21) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 2 12 Q 0 X 0 0 0 1 0 0 0 K (8.2.3. Client Interface Handler Addr) 72 712 T (ess) 261.77 712 T 1 10 Q 1 (When client programs are invoked,) 72 695.33 P 4 F 2.4 (r5) 220.3 695.33 P 3 F 1 (shall) 235.8 695.33 P 1 F 1 ( contain the address of the entry point of the) 255.25 695.33 P 3 F 1 (client interface) 444.11 695.33 P 1 (handler) 72 683.33 P 1 F 1 (. If the system is executing in Real-Mode, the value in) 102.56 683.33 P 4 F 2.4 (r5) 332.7 683.33 P 1 F 1 ( is a real address; if in V) 344.7 683.33 P 1 (irtual-Mode, the) 448.58 683.33 P 1 (address in) 72 671.33 P 4 F 2.4 (r5) 116.77 671.33 P 1 F 1 ( is a mapped virtual address.) 128.77 671.33 P 2 9 Q 0.9 (Note: this addr) 108 653 P 0.9 (ess points to the \336rst instruction of the) 167.63 653 P 0 F 0.9 (client interface handler) 323.83 653 P 2 F 0.9 (, not to a pr) 411.8 653 P 0.9 (o-) 459.99 653 P 0.9 (cedur) 108 643 P 0.9 (e descriptor) 129.83 643 P 0.9 (.) 175.64 643 P 2 12 Q (8.2.4. Client Pr) 72 619 T (ogram Arguments) 151.78 619 T 1 10 Q 1 (The calling program) 72 602.33 P 3 F 1 (may) 159.15 602.33 P 1 F 1 (pass to the client an array of bytes of arbitrary content; if this array is present, its) 179.31 602.33 P 1 (address and length) 72 590.33 P 3 F 1 (shall) 151.93 590.33 P 1 F 1 ( be passed in registers) 171.38 590.33 P 4 F 2.4 (r6) 266.64 590.33 P 1 F 1 ( and) 278.64 590.33 P 4 F 2.4 (r7) 300.08 590.33 P 1 F 1 (, respectively) 312.08 590.33 P 1 (. For programs booted directly by Open) 365.75 590.33 P 1 (Firmware, the length of this array is zero. Secondary boot programs may use this ar) 72 578.33 P 1 (gument array to pass) 419.65 578.33 P 1 (information to the programs that they boot.) 72 566.33 P 2 9 Q 0.71 (Note: The Open Firmwar) 108 548 P 0.71 (e standard makes no pr) 208.19 548 P 0.71 (ovision for specifying such an array or its) 301.35 548 P 0.9 (contents. Ther) 108 538 P 0.9 (efor) 164.23 538 P 0.9 (e, in the absence of implementation-dependent extensions, a client pr) 179.56 538 P 0.9 (o-) 450.74 538 P 0.9 (gram executed dir) 108 528 P 0.9 (ectly fr) 179.62 528 P 0.9 (om an Open Firmwar) 207.59 528 P 0.9 (e implementation will not be passed such) 293.88 528 P 0.9 (an array) 108 518 P 0.9 (. However) 141.65 518 P 0.9 (, intermediate boot pr) 180.71 518 P 0.9 (ograms that simulate or pr) 267.24 518 P 0.9 (opagate the Open) 373.66 518 P 0.9 (Firmwar) 108 508 P 0.9 (e client interface to the pr) 142.33 508 P 0.9 (ograms that they load can pr) 245.38 508 P 0.9 (ovide such an array for) 360.47 508 P 0.9 (their clients.) 108 498 P 0.9 (Note:) 108 481 P 4 F 2.16 (boot) 132.14 481 P 2 F 0.9 ( command line arguments, typically consisting of the name of a \336le to be) 153.74 481 P 0.9 (loaded by a secondary boot pr) 108 471 P 0.9 (ogram followed by \337ags selecting various secondary boot) 228.1 471 P 0.9 (and operating system options, ar) 108 461 P 0.9 (e pr) 236.69 461 P 0.9 (ovided to client pr) 252.68 461 P 0.9 (ograms via the) 324.96 461 P 5 F 2.16 ("bootargs") 386.41 461 P 2 F 0.9 ( and) 440.4 461 P 5 F 2.16 ("bootpath") 108 451 P 2 F 0.9 ( pr) 162 451 P 0.9 (operties of the) 173.99 451 P 5 F 2.16 ("/chosen") 233.42 451 P 2 F 0.9 ( node.) 282.02 451 P 2 14 Q (8.3. Caching) 72 421.67 T 1 10 Q 1 (The caches of the processor) 72 404.33 P 3 F 1 (shall) 190.57 404.33 P 1 F 1 ( be enabled when the client program is called. The I-cache shall be consistent) 210.02 404.33 P 0.95 (with the D-cache for all memory areas occupied by the client program. Memory areas allocated on behalf of the) 72 392.33 P 1 (client program) 72 380.33 P 3 F 1 (shall) 135.1 380.33 P 1 F 1 ( be marked as cacheable. Accesses to "I/O" devices \050especially) 154.55 380.33 P 1 (, to devices across "bridges"\051) 414.31 380.33 P 3 F 0.92 (shall) 72 368.33 P 1 F 0.92 ( be made with the register access words \050e.g.,) 91.45 368.33 P 4 F 2.21 (%rl@) 283.58 368.33 P 1 F 0.92 (\051. All processors in a SMP system shall have the same) 307.58 368.33 P 1 (consistent view of all memory areas \050for data references\051. No more than one processor shall have a modi\336ed) 72 356.33 P 1 (copy of the same data area in its cache when the client program is called.) 72 344.33 P 2 9 Q 0.9 (Note: If \336rmwar) 108 326 P 0.9 (e makes cachable M=0 data r) 173.12 326 P 0.9 (efer) 289.82 326 P 0.9 (ences fr) 304.64 326 P 0.9 (om differ) 335.11 326 P 0.9 (ent pr) 371.59 326 P 0.9 (ocessors on a) 395.58 326 P 0.9 (SMP system, it may have to perform additional cache management to meet this r) 108 316 P 0.9 (equir) 429.49 316 P 0.9 (e-) 449.83 316 P (ment.) 108 306 T 2 14 Q (8.4. Interrupts) 72 276.67 T 1 10 Q 1 (Open Firmware requires that interrupts be "vectored" to its handlers when it is in control of the processor; this) 72 259.33 P 1 (will occur when the User Interface is running. Client Interface calls are considered to execute in the) 72 247.33 P 1 (environment of the client, and hence, Open Firmware does not assume ownership of interrupts.) 72 235.33 P 1 (In order for Open Firmware to process interrupts in an ef) 72 216.33 P 1 (\336cient manner) 309.54 216.33 P 1 (, an area of memory for the exclusive) 367.63 216.33 P 1 (use by Open Firmware) 72 204.33 P 3 F 1 (shall) 169.87 204.33 P 1 F 1 ( be reserved by the client program at \050real\051 memory locations 0x1E0\3110x1FF) 189.32 204.33 P 1 (.) 509.19 204.33 P 1 (Open Firmware) 72 185.33 P 3 F 1 (shall) 139.54 185.33 P 1 F 1 ( save and restore the \336rst location of each interrupt that it wants to "take over". I.e.,) 158.99 185.33 P 1 (whenever Open Firmware needs the use of an interrupt, it) 72 173.33 P 3 F 1 (shall) 315 173.33 P 1 F 1 ( save the current contents of the corresponding) 334.45 173.33 P 1 (entry point and replace that location with a branch to its entry point. When Open Firmware returns control, it) 72 161.33 P 3 F 1 (shall) 72 149.33 P 1 F 1 ( restore the RAM location to its original contents.) 91.45 149.33 P 2 14 Q (8.5. Client callbacks) 72 118.67 T 1 10 Q 1 (This section de\336nes the callback mechanism that allows Open Firmware to access services exported to it by the) 72 101.33 P 1 (client program. As described in section 6.3.2 and the glossary entries for) 72 89.33 P 5 F 2.4 (callback) 376.45 89.33 P 1 F 1 ( and) 424.45 89.33 P 5 F 2.4 ($callback) 445.89 89.33 P 1 F 1 ( in [1],) 499.89 89.33 P 1 (the callback mechanism follows the same rules as those of Client interface calls. I.e., an) 72 77.33 P 3 F 1 (ar) 440.54 77.33 P 1 (gument array) 449.06 77.33 P 1 F 1 ( is) 504.22 77.33 P 52 668 54 702 R V 52 587 54 597 R V 52 389 54 411 R V 52 303 54 375 R V FMENDPAGE %%EndPage: "21" 21 %%Page: "22" 22 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (22) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 1 10 Q 0 X 0 0 0 1 0 0 0 K 1 (constructed by Open Firmware and the address of that array is passed \050via) 72 713.33 P 4 F 2.4 (r3) 383.54 713.33 P 1 F 1 (\051 to the client\325) 395.54 713.33 P 1 (s callback routine;) 454.37 713.33 P 1 (the address of the callback routine is supplied to Open Firmware by means of the) 72 701.33 P 5 F 2.4 (set-callback) 413.89 701.33 P 1 F 1 ( client call.) 485.89 701.33 P 1 (If the system is running in Real-Mode, the address of the client callback routine) 72 682.33 P 3 F 1 (shall) 407.34 682.33 P 1 F 1 ( be a real address; if it is) 426.79 682.33 P 1 (running in V) 72 670.33 P 1 (irtual-Mode, the client callback routine address) 124.51 670.33 P 3 F 1 (shall) 321.86 670.33 P 1 F 1 ( be a mapped virtual address.) 341.31 670.33 P 2 12 Q (8.5.1. Real-Mode physical memory management assist callback) 72 645 T 1 10 Q (Once the control of physical memory is transferred to the client program, Open Firmware which is running in real-) 72 628.33 T (mode) 72 616.33 T 3 F (shall) 96.72 616.33 T 1 F ( use the callback service provided by the client program to allocate physical memory) 116.17 616.33 T (. Client programs) 454.62 616.33 T (which expect Open Firmware to operate in read-mode must implement the following physical memory management) 72 604.33 T (client callback routines for Open Firmware:) 72 592.33 T 5 F (alloc-real-mem) 72 576.33 T (IN:) 108 564.33 T ([address] min_addr, [address] max_addr, size, mode) 144 564.33 T (OUT:) 108 554.33 T (error,) 144 554.33 T ([address] real_addr) 180 554.33 T 1 F -0.67 (This routine allocates a contiguous physical memory of) 108 540.33 P 3 F -0.67 (size) 327.06 540.33 P 1 F -0.67 ( bytes within the address range between) 342.06 540.33 P 3 F -0.67 (min_addr) 499.28 540.33 P 1 F (and) 108 528.33 T 3 F ( max_addr) 122.44 528.33 T 1 F (. The) 165.49 528.33 T 3 F (mode) 188.54 528.33 T 1 F ( parameter contains the WIMGxPP bits as defined in section) 210.2 528.33 T (6. A non-zero error) 454.61 528.33 T -0.38 (code) 108 516.33 P 3 F -0.38 (shall) 129 516.33 P 1 F -0.38 ( be returned if the mapping can not be performed. If error code is zero \050i.e. allocation is succeeded\051) 148.45 516.33 P (the routine returns the base address of the physical memory allocated for Open Firmware.) 108 504.33 T 2 12 Q (8.5.2. V) 72 479 T (irtual addr) 113.22 479 T (ess translation assist callbacks) 169.34 479 T 1 10 Q 1 (As mentioned in section) 72 462.33 P 1 (4.2.6., when Open Firmware is in V) 174.44 462.33 P 1 (irtual-Mode, client programs that take over control) 323.71 462.33 P 1 (of the system\325) 72 450.33 P 1 (s memory management must provide a set of callbacks that implement MMU functions. This) 130.11 450.33 P 1 (section de\336nes the input ar) 72 438.33 P 1 (guments and return values for these callbacks. The notation follows the style used in) 183.03 438.33 P 1 (chapter 6 of the Open Firmware speci\336cation [1].) 72 426.33 P 5 F (map) 72 407.33 T (IN:) 108 395.33 T ([address] phys, [address] virt, size, mode) 144 395.33 T (OUT:) 108 385.33 T (throw-code,) 144 385.33 T (error) 216 385.33 T 1 F -0.05 (This routine creates system-specific translation information; this will typically include the addition of PTEs) 108 371.33 P -0.41 (to the HTAB. If the mapping is successfully performed, a value of zero) 108 359.33 P 3 F -0.41 (shall) 390.1 359.33 P 1 F -0.41 ( be placed in the) 409.55 359.33 P 3 F -0.41 (error) 475.54 359.33 P 1 F -0.41 ( cell of the) 496.65 359.33 P (argument array; a non-zero error code) 108 347.33 T 3 F (shall) 262.38 347.33 T 1 F ( be returned in) 281.83 347.33 T 3 F (error) 342.37 347.33 T 1 F ( if the mapping can not be performed.) 363.48 347.33 T 5 F (unmap) 72 331.33 T (IN:) 108 319.33 T ([address] virt, size) 144 319.33 T (OUT:) 108 309.33 T (throw-code) 144 309.33 T 1 F (The system removes any data structures \050e.g., PTEs\051 for the virtual address range.) 108 295.33 T 5 F (translate) 72 279.33 T (IN: [address] virt) 108 267.33 T (OUT: throw-code, error, [address] real, mode) 108 257.33 T 1 F (The system attempts to compute the real address \050) 108 243.33 T 3 F (real) 307.97 243.33 T 1 F (\051 to which the virtual address \050) 324.08 243.33 T 3 F (virt) 446.28 243.33 T 1 F (\051 is mapped. If the) 460.17 243.33 T -0.23 (translation is successful, a PTE) 108 231.33 P 3 F -0.23 (shall) 234.07 231.33 P 1 F -0.23 ( be placed into the HTAB for this translation, the number of return cells) 253.52 231.33 P -0.06 (shall be four with the resulting real address returned in) 108 219.33 P 3 F -0.06 (real) 328.47 219.33 P 1 F -0.06 ( and) 344.58 219.33 P 3 F -0.06 (error) 363.9 219.33 P 1 F -0.06 ( shall be set to) 385.01 219.33 P 4 F -0.14 (false) 444.43 219.33 P 1 F -0.06 ( \0500\051. If the trans-) 474.43 219.33 P -0.36 (lation is not successful, the number of return cells) 108 207.33 P 3 F -0.36 (shall) 306.36 207.33 P 1 F -0.36 (be two and) 327.95 207.33 P 3 F -0.36 (error shall) 373.23 207.33 P 1 F -0.36 ( be set to a non-zero error code.) 415.93 207.33 P -0.49 (This call) 108 191.33 P 3 F -0.49 (shall) 144.25 191.33 P 1 F -0.49 ( be made when Open Firmware handles a DSI/ISI within the User interface. A successful result) 163.7 191.33 P -0.38 (of the translate call indicates that Open Firmware can complete the interrupted access; a failure indicates that) 108 179.33 P (an access was made to an invalid address.) 108 167.33 T 2 14 Q (9. User Interface Requir) 72 136.67 T (ements) 220.65 136.67 T 1 10 Q 1 (An implementation of Open Firmware for PowerPC) 72 119.33 P 3 F 1 (shall) 289.81 119.33 P 1 F 1 ( conform to the core requirements as speci\336ed in [1]) 309.26 119.33 P 1 (and the following PowerPC-speci\336c extensions.) 72 107.33 P 52 710 54 720 R V 52 573 54 583 R V 52 404 54 414 R V FMENDPAGE %%EndPage: "22" 22 %%Page: "23" 23 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (23) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 2 14 Q 0 X 0 0 0 1 0 0 0 K (9.1. Machine Register Access) 72 710.67 T 1 10 Q 1 (The following) 72 693.33 P 3 F 1 (user interface) 133.44 693.33 P 1 F 1 ( commands represent PowerPC registers within the) 189.71 693.33 P 3 F 1 (saved pr) 403.63 693.33 P 1 (ogram state) 438.42 693.33 P 1 F 1 (. Executing) 486.92 693.33 P 1 (the command returns the saved value of the corresponding register) 72 681.33 P 1 (. The saved value may be set by preceding) 346.78 681.33 P 1 (the command with) 72 669.33 P 2 F 1 (to) 151.94 669.33 P 1 F 1 (; the actual registers are restored to the saved values when) 160.27 669.33 P 2 F 1 (go) 405.93 669.33 P 1 F 1 ( is executed.) 415.93 669.33 P 1 (The following command displays the PowerPC CPU's) 72 650.33 P 3 F 1 (saved pr) 298.3 650.33 P 1 (ogram state) 333.09 650.33 P 1 F 1 (.) 381.59 650.33 P 4 F (.registers) 72 631.33 T 2 12 Q (9.1.1. Branch Unit Registers) 72 606 T 4 10 Q (%cr) 72 589.33 T 1 F 1 (Access saved copy of Condition Register) 90 574.33 P 1 (.) 259.15 574.33 P 4 F (%ctr) 72 556.33 T 1 F 1 (Access saved copy of Count Register) 90 541.33 P 1 (.) 243.59 541.33 P 4 F (%lr) 72 523.33 T 1 F 1 (Access saved copy of Link Register) 90 508.33 P 1 (.) 238.03 508.33 P 4 F (%msr) 72 490.33 T 1 F 1 (Access saved copy of the low order 16 bits of SRR1 register) 90 475.33 P 1 (.) 341.8 475.33 P 4 F 2.4 (%srr0) 72 457.33 P 1 F 1 (and) 110.4 457.33 P 4 F 2.4 ( %srr1) 124.84 457.33 P 1 F 1 (Access saved copy of Save/Restore Registers.) 90 442.33 P 4 F (%pc) 72 424.33 T 1 F 1 (An alias of ") 90 409.33 P 2 F 1 (%srr0) 143.46 409.33 P 1 F 1 (") 171.23 409.33 P 2 12 Q (9.1.2. Fixed-Point Registers) 72 386 T 4 10 Q 2.4 (%r0) 72 369.33 P 1 F 1 (through) 98.4 369.33 P 4 F 2.4 ( %r31) 129.51 369.33 P 1 F 1 (Access saved copies of \336xed-point registers.) 90 354.33 P 4 F (%xer) 72 336.33 T 1 F 1 (Access saved copy of XER register) 90 321.33 P 1 (.) 235.8 321.33 P 4 F 2.4 (%sprg0) 72 303.33 P 1 F 1 (through) 116.4 303.33 P 4 F 2.4 ( %sprg3) 147.51 303.33 P 1 F 1 (Access saved copies of SPRG registers.) 90 288.33 P 2 12 Q (9.1.3. Floating-Point Registers) 72 265 T 1 10 Q 1 (Unlike the other registers, the \337oating point unit registers are not normally saved, since they are not used by) 72 248.33 P 1 (Open Firmware. The following access words, therefore, access the registers directly) 72 236.33 P 1 (.) 417.09 236.33 P 4 F 2.4 (%f0) 72 217.33 P 1 F 1 (through) 98.4 217.33 P 4 F 2.4 ( %f31) 129.51 217.33 P 1 F 1 (Access \337oating point registers.) 90 202.33 P 4 F (%fpscr) 72 184.33 T 1 F 1 (Access Floating Point Status and Control Register) 90 169.33 P 1 (.) 296.01 169.33 P 2 14 Q (10. Con\336guration V) 72 140.67 T (ariables) 192.83 140.67 T 1 10 Q 1 (In addition to the standard Con\336guration V) 72 123.33 P 1 (ariables de\336ned by the core Open Firmware document [1], the) 249.66 123.33 P 1 (following Con\336guration V) 72 111.33 P 1 (ariables) 179.56 111.33 P 3 F 1 (shall) 214.16 111.33 P 1 F 1 ( be implemented for PowerPC:) 233.61 111.33 P 4 F ("little-endian?") 72 92.33 T 52 628 54 657 R V 52 136 54 176 R V FMENDPAGE %%EndPage: "23" 23 %%Page: "24" 24 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (24) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 1 10 Q 0 X 0 0 0 1 0 0 0 K 1 (This boolean variable controls the endian-mode of Open Firmware. If) 90 713.33 P 4 F 2.4 (true) 381.33 713.33 P 1 F 1 ( \050-1\051, the endian-mode is Little-) 405.33 713.33 P 1 (Endian; if) 90 703.33 P 4 F 2.4 (false) 134.22 703.33 P 1 F 1 ( \0500\051, the endian-mode is Big-Endian. The default value is implementation dependent.) 164.22 703.33 P 4 F ("real-mode?") 72 685.33 T 1 F 0.94 (This boolean variable controls the address translation mode of Open Firmware. If) 90 670.33 P 4 F 2.25 (true) 429.78 670.33 P 1 F 0.94 ( \050-1\051, the addressing) 453.78 670.33 P 1 (mode is Real-Mode; if) 90 660.33 P 4 F 2.4 (false) 186.77 660.33 P 1 F 1 ( \0500\051, the addressing mode is V) 216.77 660.33 P 1 (irtual-Mode. The default value is) 342.43 660.33 P 1 (implementation dependent.) 90 650.33 P 4 F ("real-base") 72 632.33 T 1 F 1 (This integer variable de\336nes the starting physical address to be used by Open Firmware.) 90 617.33 P 4 F ("real-size") 72 599.33 T 1 F 1 (This integer variable de\336nes the size of the physical address space which can be used by Open Firmware.) 90 584.33 P 4 F ("virt-base") 72 566.33 T 1 F 1 (This integer variable de\336nes the starting virtual memory address which can be used by Open Firmware.) 90 551.33 P 4 F ("virt-size") 72 533.33 T 1 F 1 (This integer variable de\336nes the size of the virtual address space which can be used by Open Firmware.) 90 518.33 P 4 F 2.4 ("load-base") 75.5 503.33 P 1 F 0.84 (This integer variable de\336nes the default load address for) 90 488.33 P 3 F 0.84 (client pr) 324.97 488.33 P 0.84 (ogram) 359.05 488.33 P 1 F 0.84 (s when using the) 385.16 488.33 P 4 F 2.01 (load) 457.94 488.33 P 1 F 0.84 ( method. The) 481.94 488.33 P 1 (default value is implementation dependent.) 90 478.33 P 2 14 Q (1) 72 449.67 T (1. MP Extensions) 78.23 449.67 T 1 10 Q 1 (This section speci\336es the application of Open Firmware to PowerPC multiprocessor \050MP\051 systems. An Open) 72 432.33 P 1 (Firmware implementation for an MP PowerPC system shall implement the extensions described in this section) 72 420.33 P 1 (as well as the requirements described in previous sections of this binding.) 72 408.33 P 2 14 Q (1) 72 377.67 T (1.1. The Device T) 78.23 377.67 T (r) 184.52 377.67 T (ee) 190.48 377.67 T 1 10 Q 1.09 (This section de\336nes an additional property under the "/chosen" Node for a MP extension. Refer to Section 5.1.1.) 72 360.33 P 1 (for more details about the device tree structure for a MP Con\336guration.) 72 348.33 P 2 12 Q (1) 72 323 T (1.1.1. Additional Pr) 77.34 323 T (operties) 180.47 323 T 1 10 Q 1 ("/chosen" Node Properties) 72 306.33 P 4 F ("cpu") 72 287.33 T 3 F 1 (pr) 90 272.33 P 1 (op-name) 98.52 272.33 P 1 F 1 (, identi\336es the running CPU.) 133.51 272.33 P 3 F 1 (pr) 90 254.33 P 1 (op-encode-array) 98.52 254.33 P 1 F 1 (: An integer) 165.72 254.33 P 1 (, encoded as with) 215.09 254.33 P 2 F 1 (encode-int,) 291.02 254.33 P 1 F 1 (which contains the i-handle of the CPU node) 341.46 254.33 P 1 (that is associated with the "running" CPU.) 90 244.33 P 2 14 Q (1) 72 215.67 T (1.2. Initialization) 78.23 215.67 T 1 10 Q 1 (Open Firmware shall select one processor) 72 198.33 P 1 (, using an algorithm of its choice, to be the \322master\323 processor) 244.06 198.33 P 1 (, which) 504.34 198.33 P 1 (performs the role of the single processor on a uniprocessor system, either booting the client or providing the) 72 186.33 P 1 (user interface. Open Firmware shall place all the remaining processors into stopped state, a state in which the) 72 174.33 P 1 (processor does not perform Open Firmware or client functions and does not interfere with the operation of the) 72 162.33 P 1 (master processor) 72 150.33 P 1 (. A processor in stopped state remains in that state unless and until an executing client starts it) 139.93 150.33 P 1 (using the) 72 138.33 P 5 F 2.4 (start-cpu) 112.89 138.33 P 1 F 1 ( client service de\336ned below) 166.89 138.33 P 1 (.) 284.66 138.33 P 1 (Client programs shall use the Open \336rmware) 72 119.33 P 5 F 2.4 (start-cpu) 260.92 119.33 P 1 F 1 ( client interface service to start all processors before) 314.92 119.33 P 1 (it reclaims the Open Firmware memory) 72 107.33 P 52 657 54 677 R V FMENDPAGE %%EndPage: "24" 24 %%Page: "25" 25 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (25) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 1 10 Q 0 X 0 0 0 1 0 0 0 K 1 (On machines in which a machine check on one processor is broadcast to all processors, the processors which) 72 713.33 P 1 (are either in the idle or stopped state shall not change their states due to a machine check on another processor:) 72 701.33 P 1 (Open Firmware shall not depend on the contents of the low vector \050IP=0\051 in the event of a machine check.) 72 689.33 P 1.89 (The following State Diagram depicts the relationship of the) 72 670.33 P 2 F 1.89 (Running) 329.26 670.33 P 1 F 1.89 (,) 366.5 670.33 P 2 F 1.89 (Stopped) 373.39 670.33 P 1 F 1.89 ( and) 408.4 670.33 P 2 F 1.89 (Idle States) 431.62 670.33 P 1 F 1.89 ( to each other) 478.23 670.33 P 1.89 (.) 537.5 670.33 P 1 (The) 72 658.33 P 3 F 1 (Client Interface Service) 91.05 658.33 P 1 F 1 ( Calls are shown as how to move between the states.) 188.03 658.33 P 2 9 Q (FIGURE 1) 72 636.33 T 2 10 Q (State Diagram) 126 636.33 T 2 9 Q 0.9 (Note: Open Firmwar) 108 298 P 0.9 (e's memory cannot be r) 190.62 298 P 0.9 (eclaimed by aclient if a CPU is in the) 284.04 298 P 0.9 ("stopped" or "idle" state.) 108 288 P 2 14 Q (1) 72 258.67 T (1.3. Client Interface Services) 78.23 258.67 T 1 10 Q 1.87 (The following client interface services are added for MP support on PowerPC systems. These interfaces make) 72 241.33 P 1.8 (the client program responsible for any Inter) 72 229.33 P 1.8 (-CPU communication needed for these interfaces. The rationale for) 256.47 229.33 P 1.5 (this is to architecturally separate the Inter) 72 217.33 P 1.5 (-CPU communication mechanism of the \336rmware from the client pro-) 246.3 217.33 P 1 (gram and vice versa.) 72 205.33 P 5 F (start-cpu) 72 188.33 T (IN:) 108 176.33 T (nodeid, pc, arg) 144 176.33 T (OUT:) 108 166.33 T (none) 144 166.33 T 1 F -0.42 (This client interface service starts the CPU. The) 108 152.33 P 3 F -0.42 (nodeid) 300.82 152.33 P 1 F -0.42 ( is the phandle of a node whose device_type is \322cpu\323.) 328.04 152.33 P 5 F -0.48 (Start-cpu) 108 136.33 P 1 F -0.2 ( arranges for the CPU identified by phandle in) 162 136.33 P 3 F -0.2 (nodeid) 347.67 136.33 P 1 F -0.2 ( to begin executing client code at the real) 374.89 136.33 P -0.46 (address given by the) 108 124.33 P 3 F -0.46 (pc) 190.58 124.33 P 1 F -0.46 (input with an argument,) 202.06 124.33 P 3 F -0.46 (arg,) 298.27 124.33 P 1 F -0.46 ( passed in register r3. When it begins execution, the start-) 314.66 124.33 P -0.14 (ed processor shall be in the endian mode of the client program, and in real \050not translated\051 addressing mode.) 108 112.33 P (The contents of registers other than r3 are indeterminate.) 108 100.33 T -0.08 ( A client should not call) 108 84.33 P 5 F -0.18 (start-cpu) 205.87 84.33 P 1 F -0.08 (for the processor on which it is running, effectively restarting with a) 265.69 84.33 P 72 72 540 720 C 108 311 504 633 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 7 X 0 0 0 1 0 0 0 K 90 450 49.5 51.75 186.26 545.25 G 0.5 H 2 Z 0 X 90 450 49.5 51.75 186.26 545.25 A 7 X 90 450 49.5 49.5 384.27 547.5 G 0 X 90 450 49.5 49.5 384.27 547.5 A 7 X 90 450 49.5 50 384.27 368 G 0 X 90 450 49.5 50 384.27 368 A 323.23 564.31 334.77 561 323.23 557.69 324.43 561 4 Y V 235.76 561 324.43 561 2 L N 247.3 530.69 235.76 534 247.3 537.31 246.1 534 4 Y V 334.77 534 246.1 534 2 L N 374.07 428.54 370.77 417 367.46 428.54 370.77 427.33 4 Y V 370.77 498 370.77 427.33 2 L N 394.46 486.46 397.77 498 401.07 486.46 397.77 487.67 4 Y V 397.77 417 397.77 487.67 2 L N 5 10 Q (start-cpu) 262.77 579 T (stop-self) 262.77 516 T (idle-self) 316.77 455.16 T (resume-cpu) 404.66 455.16 T 1 F (Stopped) 171 545.17 T (Running) 361.55 545.16 T (Idle) 380.45 363 T 72 72 540 720 C 0 0 612 792 C 52 185 54 195 R 0 X 0 0 0 1 0 0 0 K V 52 149 54 159 R V FMENDPAGE %%EndPage: "25" 25 %%Page: "26" 26 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (PowerPC Processor binding) 72 750 T (26) 531 750 T (March 12, 1996 Revision 1.10 DRAFT) 72 38 T 540 738 72 738 2 L 1 H 2 Z N 540 54 72 54 2 L N 558 72 585 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 558 72 585 720 R 7 X 0 0 0 1 0 0 0 K V 0 0 612 792 C 18 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 18 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 27 711 T (2) 27 699 T (3) 27 687 T (4) 27 675 T (5) 27 663 T (6) 27 651 T (7) 27 639 T (8) 27 627 T (9) 27 615 T (10) 27 603 T (11) 27 591 T (12) 27 579 T (13) 27 567 T (14) 27 555 T (15) 27 543 T (16) 27 531 T (17) 27 519 T (18) 27 507 T (19) 27 495 T (20) 27 483 T (21) 27 471 T (22) 27 459 T (23) 27 447 T (24) 27 435 T (25) 27 423 T (26) 27 411 T (27) 27 399 T (28) 27 387 T (29) 27 375 T (30) 27 363 T (31) 27 351 T (32) 27 339 T (33) 27 327 T (34) 27 315 T (35) 27 303 T (36) 27 291 T (37) 27 279 T (38) 27 267 T (39) 27 255 T (40) 27 243 T (41) 27 231 T (42) 27 219 T (43) 27 207 T (44) 27 195 T (45) 27 183 T (46) 27 171 T (47) 27 159 T (48) 27 147 T (49) 27 135 T (50) 27 123 T (51) 27 111 T (52) 27 99 T (53) 27 87 T (54) 27 75 T (55) 27 63 T 0 0 612 792 C 1 10 Q 0 X 0 0 0 1 0 0 0 K -0.1 (new pc and abandoning the only client thread. A jump or branch instruction shall be used instead to achieve) 99 713.33 P (the objective.) 99 701.33 T 5 F -0.58 (start-cpu) 99 685.33 P 1 F -0.24 ( permits more than one processor to run at the same time, enabling multi-threaded client execu-) 153 685.33 P (tion. In general, an Open Firmware client shall avoid multi-threaded operation within Open Firmware. Usu-) 99 673.33 T -0.55 (ally, this means that client threads running on different CPUs must use mutual exclusion to prevent more than) 99 661.33 P -0.62 (one processor from making client service requests at any one time. The exceptions are that a client thread may) 99 649.33 P (invoke either the) 99 637.33 T 5 F (stop-self) 168.71 637.33 T 1 F ( or) 222.71 637.33 T 5 F (idle-self) 236.04 637.33 T 1 F ( client services defined below at any time.) 290.04 637.33 T 2 9 Q 0.9 (Note: The r) 99 619 P 0.9 (esults ar) 145.12 619 P 0.9 (e unde\336ned if the CPU identi\336ed by *phandle* has alr) 178.11 619 P 0.9 (eady been) 393.83 619 P 0.9 (started \050e.g it is alr) 99 609 P 0.9 (eady running and has not exited\051 or *phandle* is not a valid package) 174.67 609 P 0.9 (handle of a CPU device node.) 99 599 P 5 10 Q (stop-self) 63 584.33 T (IN:) 99 572.33 T (none) 135 572.33 T (OUT:) 99 562.33 T (none) 135 562.33 T 1 F -0.26 (Open Firmware places the processor on which the caller was running into the "stopped" state. The client pro-) 99 548.33 P (gram is not-resumable.) 99 536.33 T 2 9 Q 0.9 (Note: When an MP client pr) 99 518 P 0.9 (ogram exits, one CPU invokes the) 212.08 518 P 5 10 Q 2.4 (exit) 348.71 518 P 2 9 Q 0.9 ( client interface ser-) 372.71 518 P 0.9 (vice, the others invoke the) 99 508 P 5 10 Q 2.4 (stop-self) 205.49 508 P 2 9 Q 0.9 ( service.) 259.49 508 P 5 10 Q (idle-self) 63 493.33 T (IN:) 99 481.33 T (none) 135 481.33 T (OUT:) 99 471.33 T (none) 135 471.33 T 1 F (Open Firmware places the CPU on which this service was invoked into an 'idle' state, saving the *current) 99 457.33 T (state* of the client program, so that the client program may be resumed.) 99 445.33 T (A processor in idle state can be resumed using) 99 429.33 T 5 F (resume-cpu) 287.02 429.33 T 1 F ( service defined below or restarted using) 347.02 429.33 T 5 F (start-cpu) 99 417.33 T 1 F (. If the processor is resumed, it executes a normal return to the client, as if its call to) 153 417.33 T 5 F (idle-) 490.72 417.33 T (self) 99 405.33 T 1 F ( had just completed.) 123 405.33 T 2 9 Q 0.79 (Note: When a client pr) 99 387 P 0.79 (ogram wants to enter the \336rmwar) 189.5 387 P 0.79 (e user interface, one CPU invokes) 323.02 387 P 0.9 (the) 99 377 P 5 10 Q 2.4 (enter) 114.15 377 P 2 9 Q 0.9 ( client interface service, the others invoke the) 144.15 377 P 5 10 Q 2.4 (idle-self) 326.56 377 P 2 9 Q 0.9 ( service. The ratio-) 380.56 377 P 0.9 (nal is that the user interface may affect the machine state in any way that it desir) 99 367 P 0.9 (es, ther) 422.69 367 P 0.9 (e-) 451.42 367 P 0.9 (for) 99 357 P 0.9 (e the client shall not depend on it.) 110.33 357 P 5 10 Q (resume-cpu) 63 342.33 T (IN:) 99 330.33 T (nodeid) 135 330.33 T (OUT:) 99 320.33 T (none) 135 320.33 T 1 F (This client interface service is used to resume an *idled* CPU. The) 99 306.33 T 3 F (nodeid) 370.9 306.33 T 1 F ( is the phandle of a CPU node in) 398.12 306.33 T (idle state.) 99 294.33 T 5 F (resume-cpu) 99 278.33 T 1 F ( arranges for that CPU to restore the CPU\325s state as saved by) 159 278.33 T 5 F (idle-self) 404.79 278.33 T 1 F ( and begin return) 458.79 278.33 T (to the client, completing the idle-self client service call that placed the CPU into idle state. The results are) 99 266.33 T -0.15 (undefined if the CPU identified by *phandle* is not in an *idle* state by a previous call to the) 99 254.33 P 5 F -0.37 (idle-self) 474.65 254.33 P 1 F (client interface service.) 99 242.33 T 2 9 Q 0.9 (Note: When the client pr) 99 224 P 0.9 (ogram is r) 197.42 224 P 0.9 (esumed via the GO \050or similar\051 user interface com-) 238.55 224 P 0.9 (mand, the client pr) 99 214 P 0.9 (ogram is r) 174.54 214 P 0.9 (esumed on the CPU which called the) 215.67 214 P 5 10 Q 2.4 (enter) 364.21 214 P 2 9 Q 0.9 ( service; the cli-) 394.21 214 P 0.9 (ent pr) 99 204 P 0.9 (ogram is r) 122.99 204 P 0.9 (esponsible for calling the) 164.12 204 P 5 10 Q 2.4 (resume-cpu) 265.22 204 P 2 9 Q 0.9 ( service to r) 325.22 204 P 0.9 (esume other idled) 372.49 204 P 0.9 (CPU's, if that is the desir) 99 194 P 0.9 (ed client pr) 199.33 194 P 0.9 (ogram behavior) 244.47 194 P 0.9 (.) 305.78 194 P 2 14 Q (1) 63 164.67 T (1.4. Br) 69.23 164.67 T (eakpoints) 112.53 164.67 T 1 10 Q 1 (If the breakpoint is taken by the \336rmware, without the client program's assistance, the other CPUs will continue) 63 147.33 P 1 (to run in the client program. The client program may \336eld the breakpoint 'trap' or 'vector' and idle the other) 63 135.33 P 1 (CPUs before entering the PROM. The platform binding document has to specify how this is done to avoid loss) 63 123.33 P 1 (of state at breakpoint time.) 63 111.33 P 43 581 45 591 R V 43 490 45 500 R V 43 339 45 349 R V FMENDPAGE %%EndPage: "26" 26 %%Page: "27" 27 612 792 0 FMBEGINPAGE [0 0 0 1 0 0 0] [ 0 1 1 0 1 0 0] [ 1 0 1 0 0 1 0] [ 1 1 0 0 0 0 1] [ 1 0 0 0 0 1 1] [ 0 1 0 0 1 0 1] [ 0 0 1 0 1 1 0] 7 FrameSetSepColors FrameNoSep 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 0 9 Q 0 X 0 0 0 1 0 0 0 K (27) 72 750 T (PowerPC Processor binding) 435.49 750 T -0.38 (March 12, 1996 Revision 1.10 DRAFT) 396.74 38 P 72 738 540 738 2 L 1 H 2 Z N 72 54 540 54 2 L N 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 27 72 54 720 C 0 0 0 1 0 0 0 K 0 0 0 1 0 0 0 K 27 72 54 720 R 7 X 0 0 0 1 0 0 0 K V 1 12 Q 0 X (1) 36 711 T (2) 36 699 T (3) 36 687 T (4) 36 675 T (5) 36 663 T (6) 36 651 T (7) 36 639 T (8) 36 627 T (9) 36 615 T (10) 36 603 T (11) 36 591 T (12) 36 579 T (13) 36 567 T (14) 36 555 T (15) 36 543 T (16) 36 531 T (17) 36 519 T (18) 36 507 T (19) 36 495 T (20) 36 483 T (21) 36 471 T (22) 36 459 T (23) 36 447 T (24) 36 435 T (25) 36 423 T (26) 36 411 T (27) 36 399 T (28) 36 387 T (29) 36 375 T (30) 36 363 T (31) 36 351 T (32) 36 339 T (33) 36 327 T (34) 36 315 T (35) 36 303 T (36) 36 291 T (37) 36 279 T (38) 36 267 T (39) 36 255 T (40) 36 243 T (41) 36 231 T (42) 36 219 T (43) 36 207 T (44) 36 195 T (45) 36 183 T (46) 36 171 T (47) 36 159 T (48) 36 147 T (49) 36 135 T (50) 36 123 T (51) 36 111 T (52) 36 99 T (53) 36 87 T (54) 36 75 T (55) 36 63 T 27 72 54 720 C 0 0 612 792 C 2 14 Q 0 X 0 0 0 1 0 0 0 K (1) 72 710.67 T (1.5. Serialization) 78.23 710.67 T 1 10 Q 1 (The \336rmware is a single threaded program, from the client program's point of view) 72 693.33 P 1 (. Only the) 416.09 693.33 P 5 F 2.4 (idle-self) 461.31 693.33 P 1 F 1 (,) 515.31 693.33 P 5 F 2.4 (stop-self) 72 681.33 P 1 F 1 (,) 126 681.33 P 5 F 2.4 (enter) 132 681.33 P 1 F 1 ( and) 162 681.33 P 5 F 2.4 (exit) 183.44 681.33 P 1 F 1 ( client interfaces may be invoked simultaneously on dif) 207.44 681.33 P 1 (ferent CPUs.) 436.9 681.33 P 1 (Furthermore, only a single CPU may invoke the) 72 669.33 P 5 F 2.4 (enter) 274.71 669.33 P 1 F 1 ( or) 304.71 669.33 P 5 F 2.4 (exit) 320.04 669.33 P 1 F 1 ( client interface at any one time. The other) 344.04 669.33 P 1 (CPUs must use the) 72 657.33 P 5 F 2.4 (idle-self) 154.34 657.33 P 1 F 1 ( or) 208.34 657.33 P 5 F 2.4 (stop-self) 223.67 657.33 P 1 F 1 ( client interface service.) 277.67 657.33 P 2 9 Q 0.9 (Note: The r) 108 639 P 0.9 (esults ar) 157.27 639 P 0.9 (e unde\336ned if the client pr) 190.26 639 P 0.9 (ogram invokes client interface services) 295.35 639 P 0.9 (including br) 108 629 P 0.9 (eakpoint traps \050other than the) 156.01 629 P 4 F 2.16 (enter/exit stop-self/idle-self) 278.25 629 P 2 F 0.9 ( case) 442.41 629 P 0.9 (listed above\051 simultaneously on mor) 108 619 P 0.9 (e than a single CPU.) 249.44 619 P 0.88 (Note: Since locking mechanisms ar) 108 602 P 0.88 (e subject to client pr) 245.34 602 P 0.88 (ogram policy) 326.66 602 P 0.88 (, the client pr) 377.29 602 P 0.88 (ogram is) 430.75 602 P 0.9 (r) 108 592 P 0.9 (esponsible for implementing any necessary mechanism to insur) 111.83 592 P 0.9 (e that it adher) 359.72 592 P 0.9 (es to this) 416.5 592 P 0.9 (policy) 108 582 P 0.9 (. Further) 130.51 582 P 0.9 (, the client pr) 165.57 582 P 0.9 (ogram should disable any pr) 219.1 582 P 0.9 (e-emption mechanism befor) 332.06 582 P 0.9 (e call-) 440.68 582 P 0.9 (ing a client interface service to avoid r) 108 572 P 0.9 (escheduling a thr) 260.36 572 P 0.9 (ead of execution in the \336rmwar) 328.01 572 P 0.9 (e) 452.08 572 P 0.9 (on a differ) 108 562 P 0.9 (ent CPU if such a mechanism exists in the client pr) 149.63 562 P 0.9 (ogram.) 352.96 562 P FMENDPAGE %%EndPage: "27" 27 %%Trailer %%BoundingBox: 0 0 612 792 %%PageOrder: Ascend %%Pages: 27 %%DocumentFonts: Times-BoldItalic %%+ Times-Roman %%+ Times-Bold %%+ Times-Italic %%+ Courier-Bold %%+ Courier %%+ Courier-Oblique %%EOF